diff --git a/CPU.qsf b/CPU.qsf index 13e6c9f..c286bda 100644 --- a/CPU.qsf +++ b/CPU.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC5C6F27C7 -set_global_assignment -name TOP_LEVEL_ENTITY Decoder_TestBench +set_global_assignment -name TOP_LEVEL_ENTITY CPU set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" @@ -66,7 +66,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Decoder_TestBench -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH CPU_TestBench -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench @@ -99,19 +99,24 @@ set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -sectio set_global_assignment -name SYSTEMVERILOG_FILE ROM.sv set_global_assignment -name SYSTEMVERILOG_FILE CPU.sv set_global_assignment -name SYSTEMVERILOG_FILE Controller.sv +set_global_assignment -name EDA_TEST_BENCH_NAME Decoder_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Decoder_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Decoder_TestBench -section_id Decoder_TestBench +set_global_assignment -name SYSTEMVERILOG_FILE Decoder.sv +set_global_assignment -name SYSTEMVERILOG_FILE Decoder_TestBench.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE CPU_TestBench.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_TEST_BENCH_NAME CPU_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id CPU_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME CPU_TestBench -section_id CPU_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE CPU_TestBench.sv -section_id CPU_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench -set_global_assignment -name EDA_TEST_BENCH_NAME Decoder_TestBench -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Decoder_TestBench -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Decoder_TestBench -section_id Decoder_TestBench -set_global_assignment -name EDA_TEST_BENCH_FILE Decoder.sv -section_id Decoder_TestBench -set_global_assignment -name SYSTEMVERILOG_FILE Decoder.sv -set_global_assignment -name SYSTEMVERILOG_FILE Decoder_TestBench.sv -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name EDA_TEST_BENCH_FILE Decoder.sv -section_id Decoder_TestBench \ No newline at end of file diff --git a/CPU_TestBench.sv b/CPU_TestBench.sv new file mode 100644 index 0000000..073aa83 --- /dev/null +++ b/CPU_TestBench.sv @@ -0,0 +1 @@ +`default_nettype none \ No newline at end of file