diff --git a/ALU.sv b/ALU.sv
index 9f3169b..a531212 100644
--- a/ALU.sv
+++ b/ALU.sv
@@ -10,14 +10,14 @@
 //              101 - SUB
 module ALU(
   input var logic[2:0] opcode,
-  input var logic[7:0] operandA,
-  input var logic[7:0] operandB,
-  output var logic[7:0] result
+  input var logic signed[7:0] operandA,
+  input var logic signed[7:0] operandB,
+  output var logic signed[7:0] result
 );
 
   // This is a var logic, because I only want a single driver.
   // It should be synthesized to a wire, as nothing is stored (hopefully?).
-  var logic[7:0] lu_result;
+  var logic signed[7:0] lu_result;
   LogicalUnit lu(
     .opcode(opcode),
     .operandA(operandA),
@@ -25,7 +25,7 @@ module ALU(
     .result(lu_result)
   );
 
-  var logic[7:0] au_result;
+  var logic signed[7:0] au_result;
   ArithmeticUnit au(
     .opcode(opcode),
     .operandA(operandA),
diff --git a/ALU_TestBench.sv b/ALU_TestBench.sv
index 7ba19f5..414a64e 100644
--- a/ALU_TestBench.sv
+++ b/ALU_TestBench.sv
@@ -3,9 +3,9 @@
 module ALU_TestBench;
 
 var logic[2:0] opcode;
-var logic[7:0] operandA;
-var logic[7:0] operandB;
-tri[7:0] result;
+var logic signed[7:0] operandA;
+var logic signed[7:0] operandB;
+tri signed[7:0] result;
 
 ALU alu(
   .opcode(opcode),
@@ -22,7 +22,7 @@ initial begin
     opcode = 3'b000;
     operandA = 8'b00000000;
     operandB = 8'b00000000;
-    #100 assert(result == 8'b00000000);
+    #20 assert(result == 8'b00000000);
 
     // First set of operands
     operandA = 8'b00000000;
diff --git a/ArithmeticUnit.sv b/ArithmeticUnit.sv
index fe293bf..5bac631 100644
--- a/ArithmeticUnit.sv
+++ b/ArithmeticUnit.sv
@@ -6,9 +6,9 @@
 //              101 - SUB
 module ArithmeticUnit(
   input var logic[2:0] opcode,
-  input var logic[7:0] operandA,
-  input var logic[7:0] operandB,
-  output var logic[7:0] result
+  input var logic signed[7:0] operandA,
+  input var logic signed[7:0] operandB,
+  output var logic signed[7:0] result
 );
 
   // If the least significant opcode bit is 0, it is an addition
diff --git a/ArithmeticUnit_TestBench.sv b/ArithmeticUnit_TestBench.sv
index 28aa27e..9ab6bef 100644
--- a/ArithmeticUnit_TestBench.sv
+++ b/ArithmeticUnit_TestBench.sv
@@ -3,9 +3,9 @@
 module ArithmeticUnit_TestBench;
 
 var logic[2:0] opcode;
-var logic[7:0] operandA;
-var logic[7:0] operandB;
-tri[7:0] result;
+var logic signed[7:0] operandA;
+var logic signed[7:0] operandB;
+tri signed[7:0] result;
 
 ArithmeticUnit au(
   .opcode(opcode),
diff --git a/ConditionalUnit.sv b/ConditionalUnit.sv
index 30fb952..d241fca 100644
--- a/ConditionalUnit.sv
+++ b/ConditionalUnit.sv
@@ -12,10 +12,11 @@
 //              111 - >= 0
 module ConditionalUnit(
   input var logic[2:0] opcode,
-  input var logic[7:0] operand,
+  input var logic signed[7:0] operand,
   output var logic result
 );
 
+  // This could be simplified significantly (basically removed), if I had ALU flags.
   always_comb case (opcode)
     3'b000: result = 0;
     3'b001: result = (operand == 0);
diff --git a/ConditionalUnit_TestBench.sv b/ConditionalUnit_TestBench.sv
new file mode 100644
index 0000000..533c66c
--- /dev/null
+++ b/ConditionalUnit_TestBench.sv
@@ -0,0 +1,133 @@
+`default_nettype none
+
+module ConditionalUnit_TestBench;
+
+var logic[2:0] opcode;
+var logic signed[7:0] operand;
+tri result;
+
+ConditionalUnit cu(
+  .opcode(opcode),
+  .operand(operand),
+  .result(result)
+);
+
+// synthesis translate_off
+initial begin
+    $timeformat(-9, 2, " ns", 20);
+
+    $display("%0t Initial Reset", $time);
+    opcode = 3'b000;
+    operand = 8'b00000000;
+    #20 assert(result == 1'b0);
+
+    // First set of operands
+    operand = 8'b00000000;
+
+    $display("%0t NEVER 1", $time);
+    opcode = 3'b000;
+    #20 assert(result == 1'b0);
+
+    $display("%0t EQUAL 1", $time);
+    opcode = 3'b001;
+    #20 assert(result == 1'b1);
+
+    $display("%0t LESS 1", $time);
+    opcode = 3'b010;
+    #20 assert(result == 1'b0);
+
+    $display("%0t LESSEQUAL 1", $time);
+    opcode = 3'b011;
+    #20 assert(result == 1'b1);
+
+    $display("%0t ALWAYS 1", $time);
+    opcode = 3'b100;
+    #20 assert(result == 1'b1);
+
+    $display("%0t NOTEQUAL 1", $time);
+    opcode = 3'b101;
+    #20 assert(result == 1'b0);
+
+    $display("%0t GREATER 1", $time);
+    opcode = 3'b110;
+    #20 assert(result == 1'b0);
+
+    $display("%0t GREATEREQUAL 1", $time);
+    opcode = 3'b111;
+    #20 assert(result == 1'b1);
+
+    // Second set of operands
+    operand = 8'b11111111;
+
+    $display("%0t NEVER 2", $time);
+    opcode = 3'b000;
+    #20 assert(result == 1'b0);
+
+    $display("%0t EQUAL 2", $time);
+    opcode = 3'b001;
+    #20 assert(result == 1'b0);
+
+    $display("%0t LESS 2", $time);
+    opcode = 3'b010;
+    #20 assert(result == 1'b1);
+
+    $display("%0t LESSEQUAL 2", $time);
+    opcode = 3'b011;
+    #20 assert(result == 1'b1);
+
+    $display("%0t ALWAYS 2", $time);
+    opcode = 3'b100;
+    #20 assert(result == 1'b1);
+
+    $display("%0t NOTEQUAL 2", $time);
+    opcode = 3'b101;
+    #20 assert(result == 1'b1);
+
+    $display("%0t GREATER 2", $time);
+    opcode = 3'b110;
+    #20 assert(result == 1'b0);
+
+    $display("%0t GREATEREQUAL 2", $time);
+    opcode = 3'b111;
+    #20 assert(result == 1'b0);
+
+    // Third set of operands
+    operand = 8'b00001111;
+
+    $display("%0t NEVER 3", $time);
+    opcode = 3'b000;
+    #20 assert(result == 1'b0);
+
+    $display("%0t EQUAL 3", $time);
+    opcode = 3'b001;
+    #20 assert(result == 1'b0);
+
+    $display("%0t LESS 3", $time);
+    opcode = 3'b010;
+    #20 assert(result == 1'b0);
+
+    $display("%0t LESSEQUAL 3", $time);
+    opcode = 3'b011;
+    #20 assert(result == 1'b0);
+
+    $display("%0t ALWAYS 3", $time);
+    opcode = 3'b100;
+    #20 assert(result == 1'b1);
+
+    $display("%0t NOTEQUAL 3", $time);
+    opcode = 3'b101;
+    #20 assert(result == 1'b1);
+
+    $display("%0t GREATER 3", $time);
+    opcode = 3'b110;
+    #20 assert(result == 1'b1);
+
+    $display("%0t GREATEREQUAL 3", $time);
+    opcode = 3'b111;
+    #20 assert(result == 1'b1);
+
+    $display("Success!");
+end
+// synthesis translate_on
+
+endmodule
\ No newline at end of file