christoph/quartus-8-bit-cpu
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Add permanent reg0 output to RegisterFile

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Christoph Urlacher
2023-03-30 00:21:31 +02:00
parent 72f7f6ca18
commit dc83546ed2
1 changed files with 2 additions and 0 deletions
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RegisterFile.sv
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@ -19,6 +19,7 @@ module RegisterFile(
output var logic[7:0] loadbus, output var logic[7:0] loadbus,
// Fixed outputs // Fixed outputs
output var logic[7:0] jumptarget,
output var logic[7:0] aluoperandA, output var logic[7:0] aluoperandA,
output var logic[7:0] aluoperandB, output var logic[7:0] aluoperandB,
output var logic[7:0] aluresult output var logic[7:0] aluresult
@ -42,6 +43,7 @@ module RegisterFile(
assign loadbus = registers[loadselector]; assign loadbus = registers[loadselector];
// Always propagate contents of ALU registers // Always propagate contents of ALU registers
assign jumptarget = registers[0];
assign aluoperandA = registers[1]; assign aluoperandA = registers[1];
assign aluoperandB = registers[2]; assign aluoperandB = registers[2];
assign aluresult = registers[3]; assign aluresult = registers[3];