From c4771484805ff018ba66649fdc34a0d982e63b9e Mon Sep 17 00:00:00 2001
From: ChUrl <christoph.urlacher@protonmail.com>
Date: Wed, 29 Mar 2023 13:57:15 +0200
Subject: [PATCH] Implement TestBench for LogicalUnit

---
 LogicalUnit_TestBench.sv | 91 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 LogicalUnit_TestBench.sv

diff --git a/LogicalUnit_TestBench.sv b/LogicalUnit_TestBench.sv
new file mode 100644
index 0000000..dcc38d1
--- /dev/null
+++ b/LogicalUnit_TestBench.sv
@@ -0,0 +1,91 @@
+`default_nettype none
+
+module LogicalUnit_TestBench;
+
+var logic[2:0] opcode;
+var logic[7:0] operandA;
+var logic[7:0] operandB;
+tri[7:0] result;
+
+LogicalUnit lu(
+  .opcode(opcode),
+  .operandA(operandA),
+  .operandB(operandB),
+  .result(result)
+);
+
+// synthesis translate_off
+initial begin
+    $timeformat(-9, 2, " ns", 20);
+
+    $display("%0t Initial Reset", $time);
+    opcode = 3'b000;
+    operandA = 8'b00000000;
+    operandB = 8'b00000000;
+    #20 assert(result == 8'b00000000);
+
+    // First set of operands
+    operandA = 8'b00000000;
+    operandB = 8'b01010101;
+
+    $display("%0t AND 1", $time);
+    opcode = 3'b000;
+    #20 assert(result == 8'b00000000);
+
+    $display("%0t OR 1", $time);
+    opcode = 3'b001;
+    #20 assert(result == 8'b01010101);
+
+    $display("%0t NAND 1", $time);
+    opcode = 3'b010;
+    #20 assert(result == 8'b11111111);
+
+    $display("%0t NOR 1", $time);
+    opcode = 3'b011;
+    #20 assert(result == 8'b10101010);
+
+    // Second set of operands
+    operandA = 8'b11111111;
+    operandB = 8'b01010101;
+
+    $display("%0t AND 2", $time);
+    opcode = 3'b000;
+    #20 assert(result == 8'b01010101);
+
+    $display("%0t OR 2", $time);
+    opcode = 3'b001;
+    #20 assert(result == 8'b11111111);
+
+    $display("%0t NAND 2", $time);
+    opcode = 3'b010;
+    #20 assert(result == 8'b10101010);
+
+    $display("%0t NOR 2", $time);
+    opcode = 3'b011;
+    #20 assert(result == 8'b00000000);
+
+    // Third set of operands
+    operandA = 8'b00001111;
+    operandB = 8'b01010101;
+
+    $display("%0t AND 3", $time);
+    opcode = 3'b000;
+    #20 assert(result == 8'b00000101);
+
+    $display("%0t OR 3", $time);
+    opcode = 3'b001;
+    #20 assert(result == 8'b01011111);
+
+    $display("%0t NAND 3", $time);
+    opcode = 3'b010;
+    #20 assert(result == 8'b11111010);
+
+    $display("%0t NOR 3", $time);
+    opcode = 3'b011;
+    #20 assert(result == 8'b10100000);
+
+    $display("Success!");
+end
+// synthesis translate_on
+
+endmodule
\ No newline at end of file