From 72f7f6ca186fe3e96b65a537c5276a8a40c899e6 Mon Sep 17 00:00:00 2001
From: ChUrl <christoph.urlacher@protonmail.com>
Date: Thu, 30 Mar 2023 00:21:15 +0200
Subject: [PATCH] Parametrize the counter bit width

---
 Counter.sv | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Counter.sv b/Counter.sv
index b42a65c..ebceed4 100644
--- a/Counter.sv
+++ b/Counter.sv
@@ -1,19 +1,20 @@
 `default_nettype none
 
-module Counter(
+module Counter
+  #(parameter WIDTH = 8)(
   input var logic clock,
   input var logic reset,
   input var logic decrement,
   input var logic setvalue,
-  input var logic[7:0] valuein,
-  output var logic[7:0] valueout
+  input var logic[WIDTH-1:0] valuein,
+  output var logic[WIDTH-1:0] valueout
 );
 
-  var logic[7:0] countervalue;
+  var logic[WIDTH-1:0] countervalue;
 
   always @(posedge clock or posedge reset) begin
     if (reset) begin
-      countervalue = 8'b0;
+      countervalue = WIDTH'(0);
     end else if (setvalue) begin
       countervalue = valuein;
     end else begin