From 0f7f2742fd11d17f9b1fa7ae7703378c405c4dec Mon Sep 17 00:00:00 2001
From: ChUrl <christoph.urlacher@protonmail.com>
Date: Wed, 29 Mar 2023 17:08:24 +0200
Subject: [PATCH] Implement Counter TestBench

---
 CPU.qsf              | 15 ++++++----
 Counter_TestBench.sv | 65 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+), 5 deletions(-)
 create mode 100644 Counter_TestBench.sv

diff --git a/CPU.qsf b/CPU.qsf
index d951bea..fad53c7 100644
--- a/CPU.qsf
+++ b/CPU.qsf
@@ -39,7 +39,7 @@
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CGXFC5C6F27C7
-set_global_assignment -name TOP_LEVEL_ENTITY RegisterFile_TestBench
+set_global_assignment -name TOP_LEVEL_ENTITY Counter_TestBench
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08  MäRZ 23, 2023"
 set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
@@ -66,7 +66,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH RegisterFile_TestBench -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Counter_TestBench -section_id eda_simulation
 set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench
@@ -92,12 +92,17 @@ set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile_TestBench.sv
 set_global_assignment -name EDA_TEST_BENCH_NAME RegisterFile_TestBench -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id RegisterFile_TestBench
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME RegisterFile_TestBench -section_id RegisterFile_TestBench
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv
 set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench
 set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench
+set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench
+set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Counter_TestBench.sv b/Counter_TestBench.sv
new file mode 100644
index 0000000..06fed56
--- /dev/null
+++ b/Counter_TestBench.sv
@@ -0,0 +1,65 @@
+`default_nettype none
+
+module Counter_TestBench;
+
+  var logic clock;
+  var logic reset;
+  var logic decrement;
+  var logic setvalue;
+  var logic[7:0] valuein;
+
+  tri[7:0] valueout;
+
+  Counter cnt(
+    .clock(clock),
+    .reset(reset),
+    .decrement(decrement),
+    .setvalue(setvalue),
+    .valuein(valuein),
+    .valueout(valueout)
+  );
+
+// synthesis translate_off
+  integer ii;
+  initial begin
+    $timeformat(-9, 2, " ns", 20);
+    
+    $display("%0t Initial Reset", $time);
+    #20 reset = 1'b1;
+    #20 reset = 1'b0;
+    assert (valueout == 1'b0);
+    
+    $display("%0t Increment 1024x", $time);
+    decrement = 1'b0;
+    for (ii = 0; ii < 1024; ii = ii + 1) begin
+      #20 clock = 1'b1;
+      #20 clock = 1'b0;
+      assert (valueout == 8'(ii + 1));
+    end
+    
+    $display("%0t Decrement 1024x", $time);
+    decrement = 1'b1;
+    for (ii = 1024; ii > 0; ii = ii - 1) begin
+      #20 clock = 1'b1;
+      #20 clock = 1'b0;
+      assert (valueout == 8'(ii - 1));
+    end
+    
+    $display("%0t Setvalue", $time);
+    decrement = 1'b0;
+    setvalue = 1'b1;
+    valuein = 8'b00001111;
+    #20 clock = 1'b1;
+    #20 clock = 1'b0;
+    assert (valueout == 8'b00001111);
+    
+    $display("%0t Reset", $time);
+    #20 reset = 1'b1;
+    #20 reset = 1'b0;
+    assert (valueout == 8'b0);
+    
+    $display("Success!");
+  end
+  
+// synthesis translate_on
+endmodule
\ No newline at end of file