christoph/quartus-8-bit-cpu
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Make Program in ROM start at address 1

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This commit is contained in:
Christoph Urlacher
2023-03-30 16:28:15 +02:00
parent dc4f25dc89
commit 0224bdc664
1 changed files with 17 additions and 10 deletions
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27
ROM.sv
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@ -5,19 +5,26 @@ module ROM(
output var logic[7:0] dataout
);
// Add and jump
always @(address) case (address)
8'b00000000: dataout = 8'b00000101; // reg0 = 5
8'b00000001: dataout = 8'b10000001; // Move reg0 to reg1
// Add and Jump
// 8'b00000000: dataout = 8'b00000101; // reg0 = 5
// 8'b00000001: dataout = 8'b10000001; // reg1 = reg0
// 8'b00000010: dataout = 8'b00001010; // reg0 = 10
// 8'b00000011: dataout = 8'b10000010; // reg2 = reg0
// 8'b00000100: dataout = 8'b01000100; // reg3 = reg1 + reg2
// 8'b00000101: dataout = 8'b10011001; // reg1 = reg3
// 8'b00000110: dataout = 8'b00001111; // reg0 = 15
// 8'b00000111: dataout = 8'b10000010; // reg2 = reg0
// 8'b00001000: dataout = 8'b01000101; // reg3 = reg1 - reg2
// 8'b00001001: dataout = 8'b00000000; // reg0 = 0
// 8'b00001010: dataout = 8'b11000001; // Jump to 0 if reg3 == 0
// Input and Output
8'b00000001: dataout = 8'b10110001; // reg1 = cpuin
8'b00000010: dataout = 8'b00001010; // reg0 = 10
8'b00000011: dataout = 8'b10000010; // Move reg0 to reg2
8'b00000011: dataout = 8'b10000010; // reg2 = reg0
8'b00000100: dataout = 8'b01000100; // reg3 = reg1 + reg2
8'b00000101: dataout = 8'b10011001; // Move reg3 to reg1
8'b00000110: dataout = 8'b00001111; // reg0 = 15
8'b00000111: dataout = 8'b10000010; // Move reg0 to reg2
8'b00001000: dataout = 8'b01000101; // reg3 = reg1 - reg2
8'b00001001: dataout = 8'b00000000; // reg0 = 0
8'b00001010: dataout = 8'b11000001; // Jump to 0 if reg3 == 0
8'b00000101: dataout = 8'b10011110; // cpuout = reg3
default: dataout = 8'b00000000;
endcase