23 lines
1.2 KiB
Plaintext
23 lines
1.2 KiB
Plaintext
Info: Start Nativelink Simulation process
|
|
|
|
========= EDA Simulation Settings =====================
|
|
|
|
Sim Mode : Gate
|
|
Family : cyclonev
|
|
Quartus root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/linux64/
|
|
Quartus sim root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/eda/sim_lib
|
|
Simulation Tool : modelsim-altera
|
|
Simulation Language : verilog
|
|
Simulation Mode : GUI
|
|
Sim Output File : 7Seg_Counter.vo
|
|
Sim SDF file : 7Seg_Counter__verilog.sdo
|
|
Sim dir : simulation/modelsim
|
|
|
|
=======================================================
|
|
|
|
Info: Starting NativeLink simulation with ModelSim-Altera software
|
|
Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl
|
|
Warning: File 7Seg_Counter_run_msim_gate_verilog.do already exists - backing up current file as 7Seg_Counter_run_msim_gate_verilog.do.bak
|
|
Info: Spawning ModelSim-Altera Simulation software
|
|
Info: NativeLink simulation flow was successful
|