48 lines
1.2 KiB
Systemverilog
48 lines
1.2 KiB
Systemverilog
`default_nettype none
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module SingleSegDriver(
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input var logic[3:0] bcdin,
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output var logic[6:0] segments
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);
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// The segments are enabled on a low logic level
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always_comb case (bcdin)
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// +----a----+
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// | |
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// f b
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// | |
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// +----g----+
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// | |
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// e c
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// | |
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// +----d----+ gfedcba
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4'b0000: segments = ~7'b0111111;
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4'b0001: segments = ~7'b0000110;
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4'b0010: segments = ~7'b1011011;
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4'b0011: segments = ~7'b1001111;
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4'b0100: segments = ~7'b1100110;
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4'b0101: segments = ~7'b1101101;
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4'b0110: segments = ~7'b1111101;
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4'b0111: segments = ~7'b0000111;
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4'b1000: segments = ~7'b1111111;
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4'b1001: segments = ~7'b1100111;
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default: segments = ~7'b0;
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endcase
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endmodule
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module SegDriver
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#(parameter integer DIGITS = 4)(
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input var logic[3:0] bcdin[DIGITS-1:0],
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output var logic[6:0] segments[DIGITS-1:0]
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);
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genvar ii;
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generate
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for (ii = 0; ii < DIGITS; ii = ii + 1) begin : generate_seg_drivers
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SingleSegDriver ssd(
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.bcdin(bcdin[ii]),
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.segments(segments[ii])
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);
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end
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endgenerate
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endmodule |