38 lines
891 B
Systemverilog
38 lines
891 B
Systemverilog
`default_nettype none
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module Counter
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#(parameter integer DIGITS = 4,
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parameter integer WIDTH = 14)(
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input var logic clock,
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input var logic reset,
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input var logic decrement,
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output var logic[WIDTH-1:0] binout
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);
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var logic[WIDTH-1:0] countervalue;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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// Reset the counter to 0
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countervalue <= '0;
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end else if (~decrement) begin
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// Increment the counter
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if (countervalue == 10**DIGITS-1) begin
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// Overflow
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countervalue <= '0;
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end else begin
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countervalue <= countervalue + 1;
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end
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end else if (decrement) begin
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// Decrement the Counter
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if (countervalue == 0) begin
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// Underflow
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countervalue <= '{10**DIGITS-1};
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end else begin
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countervalue <= countervalue - 1;
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end
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end
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end
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assign binout = countervalue;
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endmodule |