58 lines
1.1 KiB
Systemverilog
58 lines
1.1 KiB
Systemverilog
`default_nettype none
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module BinToBcd_TestBench;
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var logic clock, reset, decrement;
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tri[13:0] binout;
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Counter cnt(
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.clock(clock),
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.reset(reset),
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.decrement(decrement),
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.binout(binout)
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);
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tri[3:0] value[3:0];
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BinToBcd bcd(
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.binin(binout),
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.bcdout(value)
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);
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// synthesis translate_off
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integer ii;
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initial begin
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$timeformat(-9, 2, " ns", 20);
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$display("%0t Reset", $time);
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decrement = 0;
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#20 reset = 1;
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#20 reset = 0;
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assert (value[0] == 0);
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assert (value[1] == 0);
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assert (value[2] == 0);
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assert (value[3] == 0);
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$display("%0t Bin[1] = 0 0 0 1", $time);
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#20 clock = 1;
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#20 clock = 0;
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assert (value[0] == 1);
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assert (value[1] == 0);
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assert (value[2] == 0);
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assert (value[3] == 0);
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$display("%0t Bin[1024] = 1 0 2 4", $time);
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for (ii = 0; ii < 1023; ii = ii + 1) begin
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#20 clock = 1;
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#20 clock = 0;
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end
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assert (value[0] == 4);
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assert (value[1] == 2);
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assert (value[2] == 0);
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assert (value[3] == 1);
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$display("Success!");
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end
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// synthesis translate_on
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endmodule |