444 lines
17 KiB
TeX
444 lines
17 KiB
TeX
\chapter{Tables}
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\label{ch:tables}
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This section lists all the registers and structures required to follow \autoref{ch:implementation}.
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\clearpage
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\renewcommand{\arraystretch}{1.2} % Slightly larger row spacing
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\section{Local APIC Registers}
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\label{sec:localapicregisters}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Register Name} & \textbf{Memory Offset} \\ \hline\hline
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Local APIC ID Register & 0x20 \\ \hline
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Local APIC Version Register & 0x30 \\ \hline
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Task Priority Register & 0x80 \\ \hline
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EOI Register & 0xB0 \\ \hline
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Spurious Interrupt Vector Register & 0xF0 \\ \hline
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Error Status Register & 0x280 \\ \hline
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Interrupt Command Register[0:31] & 0x300 \\ \hline
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Interrupt Command Register[32:63] & 0x310 \\ \hline
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LVT Timer Register & 0x320 \\ \hline
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LVT LINT1 Register & 0x360 \\ \hline
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LVT Error Register & 0x370 \\ \hline
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Timer Initial Count Register & 0x380 \\ \hline
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Timer Divide Configuration Register & 0x3E0 \\ \hline
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\end{tabularx}
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\caption{Local APIC Registers used in this Implementation~\autocite[sec.~3.11.4.1]{ia32}.}
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\label{tab:lapicregs}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:23 & Reserved \\ \hline
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24:31 & Local APIC ID \\ \hline
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\end{tabularx}
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\caption{Local APIC ID Register (xApic since Pentium 4)~\autocite[sec.~3.11.4.6]{ia32}.}
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\label{tab:lapicregsid}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Local APIC Version \\ \hline
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8:15 & Reserved \\ \hline
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16:23 & Max LVT Entry \\ \hline
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24 & EOI Broadcast Suppression Support \\ \hline
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25:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Local APIC Version Register~\autocite[sec.~3.11.4.8]{ia32}.}
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\label{tab:lapicregsver}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:3 & Task-Priority Subclass \\ \hline
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4:7 & Task-Priority Class \\ \hline
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8:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Task Priority Register~\autocite[sec.~3.11.8.3.1]{ia32}.}
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\label{tab:lapicregstpr}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:31 & Send EOI Signal \\ \hline
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\end{tabularx}
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\caption{Local APIC EOI Register~\autocite[sec.~3.11.8.5]{ia32}.}
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\label{tab:lapicregseoi}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Spurious Interrupt Vector \\ \hline
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8 & APIC Software Enable/Disable \\ \hline
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9 & Focus Processor Checking \\ \hline
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10:11 & Reserved \\ \hline
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12 & EOI Broadcast Suppression \\ \hline
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13:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Spurious Interrupt Vector Register~\autocite[sec.~3.11.9]{ia32}.}
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\label{tab:lapicregssvr}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:4 & Reserved \\ \hline
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5 & Send Illegal Vector \\ \hline
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6 & Receive Illegal Vector \\ \hline
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7 & Illegal Register Access \\ \hline
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8:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Error Status Register (Pentium 4)~\autocite[sec.~3.11.5.3]{ia32}.}
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\label{tab:lapicregsesr}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Interrupt Vector \\ \hline
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8:10 & Delivery Mode \\ \hline
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11 & Destination Mode \\ \hline
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12 & Delivery Status \\ \hline
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13 & Reserved \\ \hline
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14 & Level \\ \hline
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15 & Trigger Mode \\ \hline
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16:17 & Reserved \\ \hline
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18:19 & Destination Shorthand \\ \hline
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20:55 & Reserved \\ \hline
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56:63 & Destination Field \\ \hline
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\end{tabularx}
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\caption{Interrupt Command Register~\autocite[sec.~3.11.6.1]{ia32}.}
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\label{tab:lapicregsicr}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Interrupt Vector \\ \hline
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8:11 & Reserved \\ \hline
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12 & Delivery Status \\ \hline
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13:15 & Reserved \\ \hline
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16 & Masked \\ \hline
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17:18 & Timer Mode \\ \hline
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19:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{LVT Timer Register~\autocite[sec.~3.11.5.1]{ia32}.}
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\label{tab:lapicregslvtt}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Interrupt Vector \\ \hline
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8:11 & Reserved \\ \hline
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12 & Delivery Status \\ \hline
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13:15 & Reserved \\ \hline
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16 & Masked \\ \hline
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17:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{LVT Error Register~\autocite[sec.~3.11.5.1]{ia32}.}
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\label{tab:lapicregslvterr}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Interrupt Vector \\ \hline
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8:10 & Delivery Mode \\ \hline
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11 & Reserved \\ \hline
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12 & Delivery Status \\ \hline
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13 & Pin Polarity \\ \hline
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14 & Remote IRR \\ \hline
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15 & Pin Polarity \\ \hline
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16 & Masked \\ \hline
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17:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{LVT LINT1 Register~\autocite[sec.~3.11.5.1]{ia32}.}
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\label{tab:lapicregslvtlint}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:31 & Initial Count \\ \hline
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\end{tabularx}
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\caption{Timer Initial Count Register~\autocite[sec.~3.11.5.4]{ia32}.}
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\label{tab:lapicregstimerinit}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:1 & Divider \\ \hline
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2 & Reserved \\ \hline
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3 & Divider \\ \hline
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4:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Timer Divide Configuration Register~\autocite[sec.~3.11.5.4]{ia32}.}
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\label{tab:lapicregstimerdiv}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Reserved \\ \hline
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8 & BSP Flag \\ \hline
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9 & Reserved \\ \hline
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10 & Enable x2Apic \\ \hline
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11 & Enable xApic \\ \hline
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12:35 & APIC Base Address \\ \hline
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36:63 & Reserved \\ \hline
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\end{tabularx}
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\caption{IA32\textunderscore{}
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APIC\textunderscore{}BASE MSR~\autocite[sec.~3.11.12.1]{ia32}.
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}
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\label{tab:lapicregsmsr}
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\end{table}
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\clearpage
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\section{I/O APIC Registers}
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\label{sec:ioapicregs}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Register Name} & \textbf{Memory Offset} \\ \hline\hline
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Index Register & 0x00 \\ \hline
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Data Register & 0x10 \\ \hline\hline
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\textbf{Register Name} & \textbf{Index Offset} \\ \hline\hline
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I/O APIC ID Register & 0x00 \\ \hline
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I/O APIC Version Register & 0x01 \\ \hline
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Redirection Table & 0x10:0x3F \\ \hline
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\end{tabularx}
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\caption{I/O APIC Registers used in this Implementation~\autocite[sec.~9.5]{ich5}.}
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\label{tab:ioapicregs}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Indirect Register Index \\ \hline
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\end{tabularx}
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\caption{I/O APIC Index Register~\autocite[sec.~9.5.2]{ich5}.}
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\label{tab:ioapicregsidx}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:31 & Indirect Register Data \\ \hline
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\end{tabularx}
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\caption{I/O APIC Data Register~\autocite[sec.~9.5.3]{ich5}.}
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\label{tab:ioapicregsdat}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:14 & Reserved \\ \hline
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15 & Scratchpad Bit \\ \hline
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16:23 & Reserved \\ \hline
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24:27 & I/O APIC ID \\ \hline
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28:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{I/O APIC ID Register~\autocite[sec.~9.5.6]{ich5}.}
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\label{tab:ioapicregsid}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & I/O APIC Version \\ \hline
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8:14 & Reserved \\ \hline
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15 & PRQ \\ \hline
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16:23 & Maximum Redirection Entries \\ \hline
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24:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{I/O APIC Version Register~\autocite[sec.~9.5.7]{ich5}.}
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\label{tab:ioapicregsver}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:7 & Interrupt Vector \\ \hline
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8:10 & Delivery Mode \\ \hline
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11 & Destination Mode \\ \hline
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12 & Delivery Status \\ \hline
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13 & Pin Polarity \\ \hline
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14 & Remote IRR \\ \hline
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15 & Trigger Mode \\ \hline
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16 & Masked \\ \hline
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17:47 & Reserved \\ \hline
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48:55 & Extended Destination ID \\ \hline
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56:63 & Destination \\ \hline
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\end{tabularx}
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\caption{I/O APIC REDTBL Register~\autocite[sec.~9.5.8]{ich5}.}
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\label{tab:ioapicregsredtbl}
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\end{table}
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\clearpage
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\section{System Description Tables}
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\label{sec:sdts}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:35 & MADT Header \\ \hline
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36:39 & Local APIC Base Address \\ \hline
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40:43 & Local APIC Flags \\ \hline
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44: & List of APIC Structures \\ \hline
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\end{tabularx}
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\caption{ACPI MADT~\autocite[sec.~5.2.8]{acpi1}.}
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\label{tab:madt}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:1 & APIC Structure Header \\ \hline
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2 & ACPI Processor ID \\ \hline
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3 & APIC ID \\ \hline
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4:7 & Local APIC Flags (see \autoref{tab:madtlapicflags}) \\ \hline
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\end{tabularx}
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\caption{MADT Processor Local APIC Structure~\autocite[sec.~5.2.8.1]{acpi1}.}
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\label{tab:madtlapic}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0 & Enabled \\ \hline
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1:31 & Reserved \\ \hline
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\end{tabularx}
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\caption{Local APIC Flags~\autocite[sec.~5.2.8.1]{acpi1}.}
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\label{tab:madtlapicflags}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:1 & APIC Structure Header \\ \hline
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2 & I/O APIC ID \\ \hline
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3 & Reserved \\ \hline
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4:7 & I/O APIC Base Address \\ \hline
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8:11 & I/O APIC GSI Base \\ \hline
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\end{tabularx}
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\caption{MADT I/O APIC Structure~\autocite[sec.~5.2.8.2]{acpi1}.}
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\label{tab:madtioapic}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:1 & APIC Structure Header \\ \hline
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2 & Bus \\ \hline
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3 & Source \\ \hline
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4:7 & GSI \\ \hline
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8:9 & INTI Flags (see \autoref{tab:madtintiflags}) \\ \hline
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\end{tabularx}
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\caption{MADT Interrupt Source Override Structure~\autocite[sec.~5.2.8.3.1]{acpi1}.}
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\label{tab:madtirqoverride}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Bit Number} & \textbf{Description} \\ \hline\hline
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0:1 & Pin Polarity \\ \hline
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2:3 & Trigger Mode \\ \hline
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4:11 & Reserved \\ \hline
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\end{tabularx}
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\caption{INTI Flags~\autocite[sec.~5.2.8.3.1]{acpi1}.}
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\label{tab:madtintiflags}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:1 & APIC Structure Header \\ \hline
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2:3 & INTI Flags (see \autoref{tab:madtintiflags}) \\ \hline
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4:7 & GSI \\ \hline
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\end{tabularx}
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\caption{MADT I/O APIC NMI Source~\autocite[sec.~5.2.8.3.2]{acpi1}.}
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\label{tab:madtionmi}
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\end{table}
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\begin{table}[H]
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\centering
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\begin{tabularx}{1.0\textwidth}{| X | X |}
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\hline
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\textbf{Byte Number} & \textbf{Description} \\ \hline\hline
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0:1 & APIC Structure Header \\ \hline
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2 & ACPI Processor ID \\ \hline
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3:4 & INTI Flags (see \autoref{tab:madtintiflags}) \\ \hline
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5 & Local APIC INTI \\ \hline
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\end{tabularx}
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\caption{MADT Local APIC NMI Source~\autocite[sec.~5.2.8.3.3]{acpi1}.}
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\label{tab:madtlnmi}
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\end{table}
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\cleardoublepage |