christoph/interrupt-handling-using-the-x86-apic
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Christoph Urlacher
2023-03-08 15:18:50 +01:00
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chap/implementation.tex
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@ -103,7 +103,7 @@ To be able to easily extend an APIC implementation for single-core systems to SM
\subsection{Interrupt Handling in HhuOS}
\label{subsec:apxcurrenthhuos}
In hhuOS, external interrupts are handled in two stages (see \autoref{subsec:apxcurrenthhuos} for code examples):
In hhuOS, external interrupts are handled in two stages:
\begin{enumerate}
\item After an IRQ is sent by an interrupt controller, the CPU looks up the interrupt handler address in the IDT\@.