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Add wasm tacle-bench targets

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Christoph Urlacher
2026-06-12 20:06:22 +02:00
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149
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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: interrupt.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
#ifndef _AVR_INTERRUPT_H_
#define _AVR_INTERRUPT_H_
#include <arch/io.h>
/** \name Global manipulation of the interrupt flag
The global interrupt flag is maintained in the I bit of the status
register (SREG). */
/*@{*/
/** \def sei()
\ingroup avr_interrupts
\code#include <arch/interrupt.h>\endcode
Enables interrupts by clearing the global interrupt mask. This function
actually compiles into a single line of assembly, so there is no function
call overhead. */
#define sei() __asm__ __volatile__ ("sei" ::)
/** \def cli()
\ingroup avr_interrupts
\code#include <arch/interrupt.h>\endcode
Disables all interrupts by clearing the global interrupt mask. This function
actually compiles into a single line of assembly, so there is no function
call overhead. */
#define cli() __asm__ __volatile__ ("cli" ::)
/*@}*/
#ifdef __cplusplus
extern "C" {
#endif
/** \name Allowing specific system-wide interrupts
In addition to globally enabling interrupts, each device's particular
interrupt needs to be enabled separately if interrupts for this device are
desired. While some devices maintain their interrupt enable bit inside
the device's register set, external and timer interrupts have system-wide
configuration registers.
Example:
\code
// Enable timer 1 overflow interrupts.
timer_enable_int(_BV(TOIE1));
// Do some work...
// Disable all timer interrupts.
timer_enable_int(0);
\endcode
\note Be careful when you use these functions. If you already have a
different interrupt enabled, you could inadvertantly disable it by
enabling another intterupt. */
/*@{*/
/** \ingroup avr_interrupts
\def enable_external_int(mask)
\code#include <arch/interrupt.h>\endcode
This macro gives access to the \c GIMSK register (or \c EIMSK register
if using an AVR Mega device or \c GICR register for others). Although this
macro is essentially the same as assigning to the register, it does
adapt slightly to the type of device being used. This macro is
unavailable if none of the registers listed above are defined. */
/* Define common register definition if available. */
#if defined(EIMSK)
#define __EICR EIMSK
#endif
#if defined(GIMSK)
#define __EICR GIMSK
#endif
#if defined(GICR)
#define __EICR GICR
//printf("--EICR=GICR");//FN 5-1-06
#endif
/* If common register defined, define macro. */
#if defined(__EICR) || defined(DOXYGEN)
#define enable_external_int(mask) (__EICR = mask)
#endif
/** \ingroup avr_interrupts
\code#include <arch/interrupt.h>\endcode
This function modifies the \c timsk register.
The value you pass via \c ints is device specific. */
#define __inline__ inline
static __inline__ void timer_enable_int ( unsigned char ints )
{
#ifdef TIMSK
TIMSK = ints;
#endif
}
/*@}*/
#ifdef __cplusplus
}
#endif
#endif

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/* Copyright (c) 2002,2003 Marek Michalkiewicz, Joerg Wunsch
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: io.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
/** \defgroup avr_io AVR device-specific IO definitions
\code #include <arch/io.h> \endcode
This header file includes the apropriate IO definitions for the
device that has been specified by the <tt>-mmcu=</tt> compiler
command-line switch. This is done by diverting to the appropriate
file <tt>&lt;avr/io</tt><em>XXXX</em><tt>.h&gt;</tt> which should
never be included directly. Some register names common to all
AVR devices are defined directly within <tt>&lt;avr/io.h&gt;</tt>,
but most of the details come from the respective include file.
Note that this file always includes
\code #include <arch/sfr_defs.h> \endcode
See \ref avr_sfr for the details.
Included are definitions of the IO register set and their
respective bit values as specified in the Atmel documentation.
Note that Atmel is not very consistent in its naming conventions,
so even identical functions sometimes get different names on
different devices.
Also included are the specific names useable for interrupt
function definitions as documented
\ref avr_signames "here".
Finally, the following macros are defined:
- \b RAMEND
<br>
A constant describing the last on-chip RAM location.
<br>
- \b XRAMEND
<br>
A constant describing the last possible location in RAM.
This is equal to RAMEND for devices that do not allow for
external RAM.
<br>
- \b E2END
<br>
A constant describing the address of the last EEPROM cell.
<br>
- \b FLASHEND
<br>
A constant describing the last byte address in flash ROM.
<br>
- \b SPM_PAGESIZE
<br>
For devices with bootloader support, the flash pagesize
(in bytes) to be used for the \c SPM instruction. */
#ifndef _AVR_IO_H_
#define _AVR_IO_H_
#include <arch/sfr_defs.h>
/*
Registers common to all AVR devices.
*/
#if __AVR_ARCH__ != 1
/*
AVR architecture 1 has no RAM, thus no stack pointer.
All other archs do have a stack pointer. Some devices have only
less than 256 bytes of possible RAM locations (128 Bytes of SRAM
and no option for external RAM), thus SPH is officially "reserved"
for them. We catch this case below after including the
device-specific ioXXXX.h file, by examining XRAMEND, and
#undef-ining SP and SPH in that case.
*/
/* Stack Pointer */
#define SP _SFR_IO16(0x3D)
#define SPL _SFR_IO8(0x3D)
#define SPH _SFR_IO8(0x3E)
#endif /* #if __AVR_ARCH__ != 1 */
/* Status REGister */
#define SREG _SFR_IO8(0x3F)
/* Status Register - SREG */
#define SREG_I 7
#define SREG_T 6
#define SREG_H 5
#define SREG_S 4
#define SREG_V 3
#define SREG_N 2
#define SREG_Z 1
#define SREG_C 0
/* Pointer definition */
#if __AVR_ARCH__ != 1
/* avr1 has only the Z pointer */
#define XL r26
#define XH r27
#define YL r28
#define YH r29
#endif /* #if __AVR_ARCH__ != 1 */
#define ZL r30
#define ZH r31
/*
Only few devices come without EEPROM. In order to assemble the
EEPROM library components without defining a specific device, we
keep the EEPROM-related definitions here, and catch the devices
without EEPROM (E2END == 0) below. Obviously, the EEPROM library
functions will not work for them. ;-)
*/
/* EEPROM Control Register */
#define EECR _SFR_IO8(0x1C)
/* EEPROM Data Register */
#define EEDR _SFR_IO8(0x1D)
/* EEPROM Address Register */
#define EEAR _SFR_IO16(0x1E)
#define EEARL _SFR_IO8(0x1E)
#define EEARH _SFR_IO8(0x1F)
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
#if defined (__AVR_AT94K__)
# include <arch/ioat94k.h>
#elif defined (__AVR_AT43USB320__)
# include <arch/io43u32x.h>
#elif defined (__AVR_AT43USB355__)
# include <arch/io43u35x.h>
#elif defined (__AVR_AT76C711__)
# include <arch/io76c711.h>
#elif defined (__AVR_AT86RF401__)
# include <arch/io86r401.h>
#elif defined (__AVR_ATmega128__)
# include <arch/iom128.h>
#elif defined (__AVR_AT90CAN128__)
# include <arch/iocan128.h>
#elif defined (__AVR_ATmega64__)
# include <arch/iom64.h>
#elif defined (__AVR_ATmega645__)
# include <arch/iom645.h>
#elif defined (__AVR_ATmega6450__)
# include <arch/iom6450.h>
#elif defined (__AVR_ATmega103__)
# include <arch/iom103.h>
#elif defined (__AVR_ATmega32__)
# include <arch/iom32.h>
#elif defined (__AVR_ATmega323__)
# include <arch/iom323.h>
#elif defined (__AVR_ATmega325__)
# include <arch/iom325.h>
#elif defined (__AVR_ATmega3250__)
# include <arch/iom3250.h>
#elif defined (__AVR_ATmega16__)
# include <arch/iom16.h>
#elif defined (__AVR_ATmega161__)
# include <arch/iom161.h>
#elif defined (__AVR_ATmega162__)
# include <arch/iom162.h>
#elif defined (__AVR_ATmega163__)
# include <arch/iom163.h>
#elif defined (__AVR_ATmega165__)
# include <arch/iom165.h>
#elif defined (__AVR_ATmega168__)
# include <arch/iom168.h>
#elif defined (__AVR_ATmega169__)
# include <arch/iom169.h>
#elif defined (__AVR_ATmega8__)
# include <arch/iom8.h>
#elif defined (__AVR_ATmega48__)
# include <arch/iom48.h>
#elif defined (__AVR_ATmega88__)
# include <arch/iom88.h>
#elif defined (__AVR_ATmega8515__)
# include <arch/iom8515.h>
#elif defined (__AVR_ATmega8535__)
# include <arch/iom8535.h>
#elif defined (__AVR_AT90S8535__)
# include <arch/io8535.h>
#elif defined (__AVR_AT90C8534__)
# include <arch/io8534.h>
#elif defined (__AVR_AT90S8515__)
# include <arch/io8515.h>
#elif defined (__AVR_AT90S4434__)
# include <arch/io4434.h>
#elif defined (__AVR_AT90S4433__)
# include <arch/io4433.h>
#elif defined (__AVR_AT90S4414__)
# include <arch/io4414.h>
#elif defined (__AVR_ATtiny22__)
# include <arch/iotn22.h>
#elif defined (__AVR_ATtiny26__)
# include <arch/iotn26.h>
#elif defined (__AVR_AT90S2343__)
# include <arch/io2343.h>
#elif defined (__AVR_AT90S2333__)
# include <arch/io2333.h>
#elif defined (__AVR_AT90S2323__)
# include <arch/io2323.h>
#elif defined (__AVR_AT90S2313__)
# include <arch/io2313.h>
#elif defined (__AVR_ATtiny2313__)
# include <arch/iotn2313.h>
#elif defined (__AVR_ATtiny13__)
# include <arch/iotn13.h>
/* avr1: the following only supported for assembler programs */
#elif defined (__AVR_ATtiny28__)
# include <arch/iotn28.h>
#elif defined (__AVR_AT90S1200__)
# include <arch/io1200.h>
#elif defined (__AVR_ATtiny15__)
# include <arch/iotn15.h>
#elif defined (__AVR_ATtiny12__)
# include <arch/iotn12.h>
#elif defined (__AVR_ATtiny11__)
# include <arch/iotn11.h>
#else
# if !defined(__COMPILING_AVR_LIBC__)
# warning "device type not defined"
# endif
#endif
#include <arch/portpins.h>
#if __AVR_ARCH__ != 1
# if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__)
# undef SP
# define SP _SFR_IO8(0x3D)
# undef SPH
# endif
#endif
#if E2END == 0 && !defined(__COMPILING_AVR_LIBC__)
# undef EECR
# undef EEDR
# undef EEARL
# undef EEMWE
# undef EEWE
# undef EERE
#endif
#if E2END < 0x100 && !defined(__COMPILING_AVR_LIBC__)
# undef EEAR
# if E2END > 0
# define EEAR _SFR_IO8(0x1E)
# endif
# undef EEARH
#endif
#if !defined(SIG_EEPROM_READY)
# undef EERIE
#endif
#endif /* _AVR_IO_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: iom8.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
/* avr/iom8.h - definitions for ATmega8 */
#ifndef _AVR_IOM8_H_
#define _AVR_IOM8_H_ 1
/* This file should only be included from <arch/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <arch/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom8.h"
#else
# error "Attempt to include more than one <arch/ioXXX.h> file."
#endif
/* I/O registers */
/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
#define TWBR _SFR_IO8(0x00)
#define TWSR _SFR_IO8(0x01)
#define TWAR _SFR_IO8(0x02)
#define TWDR _SFR_IO8(0x03)
/* ADC */
#define ADCW _SFR_IO16(0x04)
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x04)
#endif
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
#define ADCSR _SFR_IO8(0x06)
#define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */
#define ADMUX _SFR_IO8(0x07)
/* analog comparator */
#define ACSR _SFR_IO8(0x08)
/* USART */
#define UBRRL _SFR_IO8(0x09)
#define UCSRB _SFR_IO8(0x0A)
#define UCSRA _SFR_IO8(0x0B)
#define UDR _SFR_IO8(0x0C)
/* SPI */
#define SPCR _SFR_IO8(0x0D)
#define SPSR _SFR_IO8(0x0E)
#define SPDR _SFR_IO8(0x0F)
/* Port D */
#define PIND _SFR_IO8(0x10)
#define DDRD _SFR_IO8(0x11)
#define PORTD _SFR_IO8(0x12)
/* Port C */
#define PINC _SFR_IO8(0x13)
#define DDRC _SFR_IO8(0x14)
#define PORTC _SFR_IO8(0x15)
/* Port B */
#define PINB _SFR_IO8(0x16)
#define DDRB _SFR_IO8(0x17)
#define PORTB _SFR_IO8(0x18)
/* 0x1C..0x1F EEPROM */
#define UCSRC _SFR_IO8(0x20)
#define UBRRH _SFR_IO8(0x20)
#define WDTCR _SFR_IO8(0x21)
#define ASSR _SFR_IO8(0x22)
/* Timer 2 */
#define OCR2 _SFR_IO8(0x23)
#define TCNT2 _SFR_IO8(0x24)
#define TCCR2 _SFR_IO8(0x25)
/* Timer 1 */
#define ICR1 _SFR_IO16(0x26)
#define ICR1L _SFR_IO8(0x26)
#define ICR1H _SFR_IO8(0x27)
#define OCR1B _SFR_IO16(0x28)
#define OCR1BL _SFR_IO8(0x28)
#define OCR1BH _SFR_IO8(0x29)
#define OCR1A _SFR_IO16(0x2A)
#define OCR1AL _SFR_IO8(0x2A)
#define OCR1AH _SFR_IO8(0x2B)
#define TCNT1 _SFR_IO16(0x2C)
#define TCNT1L _SFR_IO8(0x2C)
#define TCNT1H _SFR_IO8(0x2D)
#define TCCR1B _SFR_IO8(0x2E)
#define TCCR1A _SFR_IO8(0x2F)
#define SFIOR _SFR_IO8(0x30)
#define OSCCAL _SFR_IO8(0x31)
/* Timer 0 */
#define TCNT0 _SFR_IO8(0x32)
#define TCCR0 _SFR_IO8(0x33)
#define MCUCSR _SFR_IO8(0x34)
#define MCUCR _SFR_IO8(0x35)
#define TWCR _SFR_IO8(0x36)
#define SPMCR _SFR_IO8(0x37)
#define TIFR _SFR_IO8(0x38)
#define TIMSK _SFR_IO8(0x39)
#define GIFR _SFR_IO8(0x3A)
#define GIMSK _SFR_IO8(0x3B)
#define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */
/* 0x3C reserved (OCR0?) */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/* Interrupt vectors */
#define SIG_INTERRUPT0 _VECTOR(1)
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_OUTPUT_COMPARE2 _VECTOR(3)
#define SIG_OVERFLOW2 _VECTOR(4)
#define SIG_INPUT_CAPTURE1 _VECTOR(5)
#define SIG_OUTPUT_COMPARE1A _VECTOR(6)
#define SIG_OUTPUT_COMPARE1B _VECTOR(7)
#define SIG_OVERFLOW1 _VECTOR(8)
#define SIG_OVERFLOW0 _VECTOR(9)
#define SIG_SPI _VECTOR(10)
#define SIG_UART_RECV _VECTOR(11)
#define SIG_UART_DATA _VECTOR(12)
#define SIG_UART_TRANS _VECTOR(13)
#define SIG_ADC _VECTOR(14)
#define SIG_EEPROM_READY _VECTOR(15)
#define SIG_COMPARATOR _VECTOR(16)
#define SIG_2WIRE_SERIAL _VECTOR(17)
#define SIG_SPM_READY _VECTOR(18)
#define _VECTORS_SIZE 38
/* Bit numbers */
/* GIMSK / GICR */
#define INT1 7
#define INT0 6
#define IVSEL 1
#define IVCE 0
/* GIFR */
#define INTF1 7
#define INTF0 6
/* TIMSK */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
/* bit 1 reserved (OCIE0?) */
#define TOIE0 0
/* TIFR */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
/* bit 1 reserved (OCF0?) */
#define TOV0 0
/* SPMCR */
#define SPMIE 7
#define RWWSB 6
/* bit 5 reserved */
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* TWCR */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
/* bit 1 reserved (TWI_TST?) */
#define TWIE 0
/* TWAR */
#define TWA6 7
#define TWA5 6
#define TWA4 5
#define TWA3 4
#define TWA2 3
#define TWA1 2
#define TWA0 1
#define TWGCE 0
/* TWSR */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
/* bit 2 reserved */
#define TWPS1 1
#define TWPS0 0
/* MCUCR */
#define SE 7
#define SM2 6
#define SM1 5
#define SM0 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* MCUCSR */
/* bits 7-4 reserved */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* SFIOR */
/* bits 7-5 reserved */
#define ADHSM 4
#define ACME 3
#define PUD 2
#define PSR2 1
#define PSR10 0
/* TCCR0 */
/* bits 7-3 reserved */
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR2 */
#define FOC2 7
#define WGM20 6
#define COM21 5
#define COM20 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0
/* ASSR */
/* bits 7-4 reserved */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define WGM11 1
#define WGM10 0
/* TCCR1B */
#define ICNC1 7
#define ICES1 6
/* bit 5 reserved */
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0
/* WDTCR */
/* bits 7-5 reserved */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* UBRRH */
#define URSEL 7
/* UCSRC */
#define URSEL 7
#define UMSEL 6
#define UPM1 5
#define UPM0 4
#define USBS 3
#define UCSZ1 2
#define UCSZ0 1
#define UCPOL 0
/* PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* PORTC */
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* DDRC */
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* PINC */
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPSR */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* UCSRA */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
#define PE 2
#define U2X 1
#define MPCM 0
/* UCSRB */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define UCSZ2 2
#define RXB8 1
#define TXB8 0
/* ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* ADCSR / ADCSRA */
#define ADEN 7
#define ADSC 6
#define ADFR 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
/* bit 4 reserved */
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* Constants */
#define SPM_PAGESIZE 64
#define RAMEND 0x45F
#define XRAMEND 0x45F
#define E2END 0x1FF
#define FLASHEND 0x1FFF
#endif /* _AVR_IOM8_H_ */

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/* Copyright (c) 2003 Theodore A. Roth
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: portpins.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
#ifndef _AVR_PORTPINS_H_
#define _AVR_PORTPINS_H_ 1
/* This file should only be included from <arch/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <arch/io.h> instead of this file."
#endif
/* Define Generic PORTn, DDn, and PINn values. */
/* Port Data Register (generic) */
#define PORT7 7
#define PORT6 6
#define PORT5 5
#define PORT4 4
#define PORT3 3
#define PORT2 2
#define PORT1 1
#define PORT0 0
/* Port Data Direction Register (generic) */
#define DD7 7
#define DD6 6
#define DD5 5
#define DD4 4
#define DD3 3
#define DD2 2
#define DD1 1
#define DD0 0
/* Port Input Pins (generic) */
#define PIN7 7
#define PIN6 6
#define PIN5 5
#define PIN4 4
#define PIN3 3
#define PIN2 2
#define PIN1 1
#define PIN0 0
/* Define PORTxn values for all possible port pins. */
/* PORT A */
#if defined(PA0)
# define PORTA0 PA0
#endif
#if defined(PA1)
# define PORTA1 PA1
#endif
#if defined(PA2)
# define PORTA2 PA2
#endif
#if defined(PA3)
# define PORTA3 PA3
#endif
#if defined(PA4)
# define PORTA4 PA4
#endif
#if defined(PA5)
# define PORTA5 PA5
#endif
#if defined(PA6)
# define PORTA6 PA6
#endif
#if defined(PA7)
# define PORTA7 PA7
#endif
/* PORT B */
#if defined(PB0)
# define PORTB0 PB0
#endif
#if defined(PB1)
# define PORTB1 PB1
#endif
#if defined(PB2)
# define PORTB2 PB2
#endif
#if defined(PB3)
# define PORTB3 PB3
#endif
#if defined(PB4)
# define PORTB4 PB4
#endif
#if defined(PB5)
# define PORTB5 PB5
#endif
#if defined(PB6)
# define PORTB6 PB6
#endif
#if defined(PB7)
# define PORTB7 PB7
#endif
/* PORT C */
#if defined(PC0)
# define PORTC0 PC0
#endif
#if defined(PC1)
# define PORTC1 PC1
#endif
#if defined(PC2)
# define PORTC2 PC2
#endif
#if defined(PC3)
# define PORTC3 PC3
#endif
#if defined(PC4)
# define PORTC4 PC4
#endif
#if defined(PC5)
# define PORTC5 PC5
#endif
#if defined(PC6)
# define PORTC6 PC6
#endif
#if defined(PC7)
# define PORTC7 PC7
#endif
/* PORT D */
#if defined(PD0)
# define PORTD0 PD0
#endif
#if defined(PD1)
# define PORTD1 PD1
#endif
#if defined(PD2)
# define PORTD2 PD2
#endif
#if defined(PD3)
# define PORTD3 PD3
#endif
#if defined(PD4)
# define PORTD4 PD4
#endif
#if defined(PD5)
# define PORTD5 PD5
#endif
#if defined(PD6)
# define PORTD6 PD6
#endif
#if defined(PD7)
# define PORTD7 PD7
#endif
/* PORT E */
#if defined(PE0)
# define PORTE0 PE0
#endif
#if defined(PE1)
# define PORTE1 PE1
#endif
#if defined(PE2)
# define PORTE2 PE2
#endif
#if defined(PE3)
# define PORTE3 PE3
#endif
#if defined(PE4)
# define PORTE4 PE4
#endif
#if defined(PE5)
# define PORTE5 PE5
#endif
#if defined(PE6)
# define PORTE6 PE6
#endif
#if defined(PE7)
# define PORTE7 PE7
#endif
/* PORT F */
#if defined(PF0)
# define PORTF0 PF0
#endif
#if defined(PF1)
# define PORTF1 PF1
#endif
#if defined(PF2)
# define PORTF2 PF2
#endif
#if defined(PF3)
# define PORTF3 PF3
#endif
#if defined(PF4)
# define PORTF4 PF4
#endif
#if defined(PF5)
# define PORTF5 PF5
#endif
#if defined(PF6)
# define PORTF6 PF6
#endif
#if defined(PF7)
# define PORTF7 PF7
#endif
/* PORT G */
#if defined(PG0)
# define PORTG0 PG0
#endif
#if defined(PG1)
# define PORTG1 PG1
#endif
#if defined(PG2)
# define PORTG2 PG2
#endif
#if defined(PG3)
# define PORTG3 PG3
#endif
#if defined(PG4)
# define PORTG4 PG4
#endif
#if defined(PG5)
# define PORTG5 PG5
#endif
#if defined(PG6)
# define PORTG6 PG6
#endif
#if defined(PG7)
# define PORTG7 PG7
#endif
#endif /* _AVR_PORTPINS_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz <marekm@amelek.gda.pl>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* avr/sfr_defs.h - macros for accessing AVR special function registers */
/* $Id: sfr_defs.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
#ifndef _AVR_SFR_DEFS_H_
#define _AVR_SFR_DEFS_H_ 1
/** \defgroup avr_sfr_notes Additional notes from <arch/sfr_defs.h>
\ingroup avr_sfr
The \c <arch/sfr_defs.h> file is included by all of the \c <arch/ioXXXX.h>
files, which use macros defined here to make the special function register
definitions look like C variables or simple constants, depending on the
<tt>_SFR_ASM_COMPAT</tt> define. Some examples from \c <arch/iom128.h> to
show how to define such macros:
\code
#define PORTA _SFR_IO8(0x1b)
#define TCNT1 _SFR_IO16(0x2c)
#define PORTF _SFR_MEM8(0x61)
#define TCNT3 _SFR_MEM16(0x88)
\endcode
If \c _SFR_ASM_COMPAT is not defined, C programs can use names like
<tt>PORTA</tt> directly in C expressions (also on the left side of
assignment operators) and GCC will do the right thing (use short I/O
instructions if possible). The \c __SFR_OFFSET definition is not used in
any way in this case.
Define \c _SFR_ASM_COMPAT as 1 to make these names work as simple constants
(addresses of the I/O registers). This is necessary when included in
preprocessed assembler (*.S) source files, so it is done automatically if
\c __ASSEMBLER__ is defined. By default, all addresses are defined as if
they were memory addresses (used in \c lds/sts instructions). To use these
addresses in \c in/out instructions, you must subtract 0x20 from them.
For more backwards compatibility, insert the following at the start of your
old assembler source file:
\code
#define __SFR_OFFSET 0
\endcode
This automatically subtracts 0x20 from I/O space addresses, but it's a
hack, so it is recommended to change your source: wrap such addresses in
macros defined here, as shown below. After this is done, the
<tt>__SFR_OFFSET</tt> definition is no longer necessary and can be removed.
Real example - this code could be used in a boot loader that is portable
between devices with \c SPMCR at different addresses.
\verbatim
<arch/iom163.h>: #define SPMCR _SFR_IO8(0x37)
<arch/iom128.h>: #define SPMCR _SFR_MEM8(0x68)
\endverbatim
\code
#if _SFR_IO_REG_P(SPMCR)
out _SFR_IO_ADDR(SPMCR), r24
#else
sts _SFR_MEM_ADDR(SPMCR), r24
#endif
\endcode
You can use the \c in/out/cbi/sbi/sbic/sbis instructions, without the
<tt>_SFR_IO_REG_P</tt> test, if you know that the register is in the I/O
space (as with \c SREG, for example). If it isn't, the assembler will
complain (I/O address out of range 0...0x3f), so this should be fairly
safe.
If you do not define \c __SFR_OFFSET (so it will be 0x20 by default), all
special register addresses are defined as memory addresses (so \c SREG is
0x5f), and (if code size and speed are not important, and you don't like
the ugly #if above) you can always use lds/sts to access them. But, this
will not work if <tt>__SFR_OFFSET</tt> != 0x20, so use a different macro
(defined only if <tt>__SFR_OFFSET</tt> == 0x20) for safety:
\code
sts _SFR_ADDR(SPMCR), r24
\endcode
In C programs, all 3 combinations of \c _SFR_ASM_COMPAT and
<tt>__SFR_OFFSET</tt> are supported - the \c _SFR_ADDR(SPMCR) macro can be
used to get the address of the \c SPMCR register (0x57 or 0x68 depending on
device). */
#ifdef __ASSEMBLER__
#define _SFR_ASM_COMPAT 1
#endif
#ifndef __ASSEMBLER__
/* These only work in C programs. */
#include <inttypes.h>
#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr))
#define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr))
#endif
#if _SFR_ASM_COMPAT
#ifndef __SFR_OFFSET
/* Define as 0 before including this file for compatibility with old asm
sources that don't subtract __SFR_OFFSET from symbolic I/O addresses. */
#define __SFR_OFFSET 0x20
#endif
#if (__SFR_OFFSET != 0) && (__SFR_OFFSET != 0x20)
#error "__SFR_OFFSET must be 0 or 0x20"
#endif
#define _SFR_MEM8(mem_addr) (mem_addr)
#define _SFR_MEM16(mem_addr) (mem_addr)
#define _SFR_IO8(io_addr) ((io_addr) + __SFR_OFFSET)
#define _SFR_IO16(io_addr) ((io_addr) + __SFR_OFFSET)
#define _SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET)
#define _SFR_MEM_ADDR(sfr) (sfr)
#define _SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET)
#if (__SFR_OFFSET == 0x20)
/* No need to use ?: operator, so works in assembler too. */
#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr)
#elif !defined(__ASSEMBLER__)
#define _SFR_ADDR(sfr) (_SFR_IO_REG_P(sfr) ? (_SFR_IO_ADDR(sfr) + 0x20) : _SFR_MEM_ADDR(sfr))
#endif
#else /* !_SFR_ASM_COMPAT */
#define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr)
#define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr)
#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + 0x20)
#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + 0x20)
#define _SFR_MEM_ADDR(sfr) ((uint16_t) &(sfr))
#define _SFR_IO_ADDR(sfr) (_SFR_MEM_ADDR(sfr) - 0x20)
#define _SFR_IO_REG_P(sfr) (_SFR_MEM_ADDR(sfr) < 0x60)
#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr)
#endif /* !_SFR_ASM_COMPAT */
#define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr))
#define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr))
/** \name Bit manipulation */
/*@{*/
/** \def _BV
\ingroup avr_sfr
\code #include <arch/io.h>\endcode
Converts a bit number into a byte value.
\note The bit shift is performed by the compiler which then inserts the
result into the code. Thus, there is no run-time overhead when using
_BV(). */
#define _BV(bit) (1 << (bit))
/*@}*/
#ifndef _VECTOR
#define _VECTOR(N) __vector_ ## N
#endif
#ifndef __ASSEMBLER__
/** \name IO register bit manipulation */
/*@{*/
/** \def bit_is_set
\ingroup avr_sfr
\code #include <arch/io.h>\endcode
Test whether bit \c bit in IO register \c sfr is set.
This will return a 0 if the bit is clear, and non-zero
if the bit is set. */
#define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit))
/** \def bit_is_clear
\ingroup avr_sfr
\code #include <arch/io.h>\endcode
Test whether bit \c bit in IO register \c sfr is clear.
This will return non-zero if the bit is clear, and a 0
if the bit is set. */
#define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit)))
/** \def loop_until_bit_is_set
\ingroup avr_sfr
\code #include <arch/io.h>\endcode
Wait until bit \c bit in IO register \c sfr is set. */
#define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit))
/** \def loop_until_bit_is_clear
\ingroup avr_sfr
\code #include <arch/io.h>\endcode
Wait until bit \c bit in IO register \c sfr is clear. */
#define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit))
/*@}*/
#endif /* !__ASSEMBLER__ */
#endif /* _SFR_DEFS_H_ */

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/* Copyright (c) 2002, Marek Michalkiewicz
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id: signal.h,v 1.1 2011-01-25 09:40:04 plazar Exp $ */
#ifndef _AVR_SIGNAL_H_
#define _AVR_SIGNAL_H_
/** \name Macros for writing interrupt handler functions */
/*@{*/
/** \def SIGNAL(signame)
\ingroup avr_interrupts
\code#include <arch/signal.h>\endcode
Introduces an interrupt handler function that runs with global interrupts
initially disabled. */
#ifdef __cplusplus
#define SIGNAL(signame) \
extern "C" void signame(void); \
void signame (void) __attribute__ ((signal)); \
void signame (void)
#else
#define SIGNAL(signame) \
void signame (void)
#endif
/** \def INTERRUPT(signame)
\ingroup avr_interrupts
\code#include <arch/signal.h>\endcode
Introduces an interrupt handler function that runs with global interrupts
initially enabled. This allows interrupt handlers to be interrupted. */
#ifdef __cplusplus
#define INTERRUPT(signame) \
extern "C" void signame(void); \
void signame (void) __attribute__ ((interrupt)); \
void signame (void)
#else
#define INTERRUPT(signame) \
void signame (void) __attribute__ ((interrupt)); \
void signame (void)
#endif
/** \def EMPTY_INTERRUPT(signame)
\ingroup avr_interrupts
\code#include <arch/signal.h>\endcode
Defines an empty interrupt handler function. This will not generate
any prolog or epilog code and will only return from the ISR. Do not
define a function body as this will define it for you.
Example:
\code EMPTY_INTERRUPT(SIG_ADC);\endcode */
#ifdef __cplusplus
#define EMPTY_INTERRUPT(signame) \
extern "C" void signame(void); \
void signame (void) __attribute__ ((naked)); \
void signame (void) { __asm__ __volatile__ ("reti" ::); }
#else
#define EMPTY_INTERRUPT(signame) \
void signame (void) __attribute__ ((naked)); \
void signame (void) { __asm__ __volatile__ ("reti" ::); }
#endif
/*@}*/
#endif /* _AVR_SIGNAL_H_ */