bedb9c2eb2
The InstructionImporter does disassemble the binary and generate read traces for every instruction byte executed. Change-Id: I6b8697c711c009e106ed733c74c6ff8f9bbf8ac5
81 lines
2.5 KiB
C++
81 lines
2.5 KiB
C++
#ifndef __puma
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#include <sstream>
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#include <iostream>
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#include "InstructionImporter.hpp"
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#include "util/Logger.hpp"
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using namespace llvm;
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using namespace llvm::object;
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using namespace fail;
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static Logger LOG("InstructionImporter");
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bool InstructionImporter::handle_ip_event(fail::simtime_t curtime, instruction_count_t instr,
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const Trace_Event &ev) {
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if (!binary) {
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/* Disassemble the binary if necessary */
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llvm::InitializeAllTargetInfos();
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llvm::InitializeAllTargetMCs();
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llvm::InitializeAllDisassemblers();
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if (error_code ec = createBinary(m_elf->getFilename(), binary)) {
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LOG << m_elf->getFilename() << "': " << ec.message() << ".\n";
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return false;
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}
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ObjectFile *obj = dyn_cast<ObjectFile>(binary.get());
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disas.reset(new LLVMDisassembler(obj));
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disas->disassemble();
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LLVMDisassembler::InstrMap &instr_map = disas->getInstrMap();
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LOG << "instructions disassembled: " << instr_map.size() << " Triple: " << disas->GetTriple() << std::endl;
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}
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const LLVMDisassembler::InstrMap &instr_map = disas->getInstrMap();
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const LLVMDisassembler::Instr &opcode = instr_map.at(ev.ip());
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address_t from = ev.ip(), to = ev.ip() + opcode.length;
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// Iterate over all accessed bytes
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for (address_t data_address = from; data_address < to; ++data_address) {
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// skip events outside a possibly supplied memory map
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if (m_mm && !m_mm->isMatching(data_address)) {
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continue;
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}
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margin_info_t left_margin = getOpenEC(data_address);
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margin_info_t right_margin;
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right_margin.time = curtime;
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right_margin.dyninstr = instr; // !< The current instruction
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right_margin.ip = ev.ip();
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// skip zero-sized intervals: these can occur when an instruction
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// accesses a memory location more than once (e.g., INC, CMPXCHG)
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if (left_margin.dyninstr > right_margin.dyninstr) {
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continue;
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}
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// we now have an interval-terminating R/W event to the memaddr
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// we're currently looking at; the EC is defined by
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// data_address, dynamic instruction start/end, the absolute PC at
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// the end, and time start/end
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access_info_t access;
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access.access_type = 'R'; // instruction fetch is always a read
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access.data_address = data_address;
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access.data_width = 1; // exactly one byte
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if (!add_trace_event(left_margin, right_margin, access)) {
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LOG << "add_trace_event failed" << std::endl;
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return false;
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}
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// next interval must start at next instruction; the aforementioned
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// skipping mechanism wouldn't work otherwise
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newOpenEC(data_address, curtime + 1, instr + 1, ev.ip());
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}
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return true;
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}
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#endif // !__puma
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