b70b6fb43a
"failstar" sounds like a name for a cruise liner from the 80s. As "*" isn't a desirable part of directory names, just name the whole thing "fail/", the core parts being stored in "fail/core/". Additionally fixing two build system dependency issues: - missing jobserver -> protomessages dependency - broken bochs -> fail dependency (add_custom_target DEPENDS only allows plain file dependencies ... cmake for the win) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@956 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
147 lines
4.5 KiB
Plaintext
147 lines
4.5 KiB
Plaintext
#ifndef __MEM_EVENTS_AH__
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#define __MEM_EVENTS_AH__
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#include <iostream>
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#include "../../AspectConfig.hpp"
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#if CONFIG_EVENT_MEMREAD == 1 || CONFIG_EVENT_MEMWRITE == 1
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#include "../../../bochs/bochs.h"
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#include "../../../bochs/cpu/cpu.h"
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#include "../SALInst.hpp"
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#include "bochs_helpers.hpp"
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// FIXME we currently assume a "flat" memory model and ignore the segment
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// parameter of all memory accesses
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// TODO instruction fetch?
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// TODO warn on uncovered memory accesses
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aspect MemEvents
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{
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sal::address_t rmw_address;
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pointcut write_methods() =
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"% ...::bx_cpu_c::write_virtual_%(...)" && // -> access32/64.cc
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// not an actual memory access:
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!"% ...::bx_cpu_c::write_virtual_checks(...)";
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pointcut write_methods_RMW() =
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"% ...::bx_cpu_c::write_RMW_virtual_%(...)";
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pointcut write_methods_new_stack() =
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"% ...::bx_cpu_c::write_new_stack_%(...)" && // -> access32.cc
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!"% ...::bx_cpu_c::write_new_stack_%_64(...)";
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pointcut write_methods_new_stack_64() =
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"% ...::bx_cpu_c::write_new_stack_%_64(...)"; // -> access64.cc
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pointcut write_methods_system() =
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"% ...::bx_cpu_c::system_write_%(...)"; // -> access.cc
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// FIXME not covered:
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/* "% ...::bx_cpu_c::v2h_write_byte(...)"; // -> access.cc */
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pointcut read_methods() =
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"% ...::bx_cpu_c::read_virtual_%(...)" &&
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// sizeof() doesn't work here (see next pointcut)
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!"% ...::bx_cpu_c::read_virtual_dqword_%(...)" && // -> access32/64.cc
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// not an actual memory access:
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!"% ...::bx_cpu_c::read_virtual_checks(...)";
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pointcut read_methods_dqword() =
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"% ...::bx_cpu_c::read_virtual_dqword_%(...)"; // -> access32/64.cc
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pointcut read_methods_RMW() =
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"% ...::bx_cpu_c::read_RMW_virtual_%(...)";
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pointcut read_methods_system() =
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"% ...::bx_cpu_c::system_read_%(...)"; // -> access.cc
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// FIXME not covered:
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/* "% ...::bx_cpu_c::v2h_read_byte(...)"; // -> access.cc */
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//
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// Fire a memory-write-event each time the guest system requests
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// to write data to RAM:
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//
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// Event source: "memory write access"
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//
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#if CONFIG_EVENT_MEMWRITE == 1
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advice execution (write_methods()) : after () {
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<1>()), sizeof(*(tjp->arg<2>())), true,
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getCPU(tjp->that())->prev_rip);
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}
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advice execution (write_methods_RMW()) : after () {
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sal::simulator.onMemoryAccessEvent(
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rmw_address, sizeof(*(tjp->arg<0>())), true,
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getCPU(tjp->that())->prev_rip);
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}
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advice execution (write_methods_new_stack()) : after () {
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std::cerr << "WOOOOOT write_methods_new_stack" << std::endl;
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<1>()), sizeof(*(tjp->arg<3>())), true,
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getCPU(tjp->that())->prev_rip);
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}
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advice execution (write_methods_new_stack_64()) : after () {
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std::cerr << "WOOOOOT write_methods_new_stack_64" << std::endl;
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<0>()), sizeof(*(tjp->arg<2>())), true,
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getCPU(tjp->that())->prev_rip);
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}
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advice execution (write_methods_system()) : after () {
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// We don't do anything here for now: This type of memory
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// access is used when the hardware itself needs to access
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// memory (e.g., to read vectors from the interrupt vector
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// table).
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/*
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<0>()), sizeof(*(tjp->arg<1>())), true,
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getCPU(tjp->that())->prev_rip);
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*/
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}
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#endif
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//
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// Fire a memory-read-event each time the guest system requests
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// to read data in RAM:
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//
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// Event source: "memory read access"
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//
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#if CONFIG_EVENT_MEMREAD == 1
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advice execution (read_methods()) : before () {
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<1>()), sizeof(*(tjp->result())), false,
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getCPU(tjp->that())->prev_rip);
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}
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advice execution (read_methods_dqword()) : before () {
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<1>()), 16, false,
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getCPU(tjp->that())->prev_rip);
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}
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#endif
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advice execution (read_methods_RMW()) : before () {
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rmw_address = *(tjp->arg<1>());
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#if CONFIG_EVENT_MEMREAD == 1
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<1>()), sizeof(*(tjp->result())), false,
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getCPU(tjp->that())->prev_rip);
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#endif
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}
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#if CONFIG_EVENT_MEMREAD == 1
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advice execution (read_methods_system()) : before () {
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// We don't do anything here for now: This type of memory
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// access is used when the hardware itself needs to access
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// memory (e.g., to read vectors from the interrupt vector
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// table).
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/*
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sal::simulator.onMemoryAccessEvent(
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*(tjp->arg<0>()), sizeof(*(tjp->result())), false,
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getCPU(tjp->that())->prev_rip);
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*/
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}
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#endif
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};
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#endif // CONFIG_EVENT_MEMACCESS
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#endif /* __MEM_EVENTS_AH__ */
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