e5fe9dd525
This adds an interface for a backend-specific notion of time, e.g. CPU cycles since simulator start, and a concrete implementation for the Bochs backend. This is needed to record CPU idle times (e.g., HLT instruction), and for target backends capable of more timing-accurate execution. This change also modifies the tracing plugin to add the time to all trace events. Change-Id: I93ac1d54c07f32b0b8f84f333417741d8e9c8288
Some hints on memory-access tracing in Bochs:
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- Instruction fetches: no memory accesses!
- INC ${MEM_ADDR} (increment in memory): a read and a write access
- CALL ${INSTR_ADDR} (call function): a single write access
- PUSH %{REG} (push on stack): dito
- PUSHF (push on stack): dito
- INT ${INTERRUPT#} (interrupt trigger): 3 write accesses