7ae8b6b09d
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1864 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
372 lines
14 KiB
C++
372 lines
14 KiB
C++
#ifndef __L4SYS_ALUINSTR_HPP__
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#define __L4SYS_ALUINSTR_HPP__
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#include <map>
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#include <vector>
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#include <string>
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#include <stdlib.h>
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#include "config.h"
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#include "cpu/instr.h"
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/**
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* \enum X86AluClass
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*
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* \brief An attempt to order X86 ALU instructions.
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*
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* An attempt to order X86 ALU instructions.
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* Each instruction class contains instructions
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* of roughly equal length and operands, so that
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* all the bxInstruction_c structures residing within
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* one class contain the same member fields (except for
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* b1, rm and the execute function pointers).
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*/
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enum X86AluClass {
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ALU_UNDEF = 0,
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ALU_GENERIC,
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ALU_RM8,
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ALU_RM16,
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ALU_RM32,
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ALU_IMM8,
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ALU_IMM16,
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ALU_IMM32,
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ALU_IMM8_RM8,
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ALU_IMM8_RM16,
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ALU_IMM8_RM32,
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ALU_IMM16_RM16,
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ALU_IMM32_RM32
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};
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/**
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* \struct BochsALUInstr
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*
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* A struct describing a specific x86
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* ALU instruction in terms of Bochs.
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*/
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struct BochsALUInstr {
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/**
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* the Bochs operation ID (confusingly called ia_opcode
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* in bxInstruction_c), pointing to several bits of information,
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* for instance what simulator function to execute
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*/
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Bit16u bochs_operation;
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/**
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* the x86 opcode, as stored by Bochs (known as b1 in bxInstruction_c)
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*/
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Bit8u opcode;
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/**
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* the reg part of the modr/m field (known as "nnn" in bxInstruction_c)
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* it is used to
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* a) further subdivide the functionality of a given opcode (reg < REG_COUNT)
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* b) specify a register the instruction is supposed to use (reg = REG_COUNT)
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* In this class, a value greater than REG_COUNT marks this field unused.
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*/
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Bit8u reg;
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/**
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* the register offset of the instruction byte of this instruction
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* Some x86 instructions, like INC register, add a register offset
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* to their opcode. This offset is stored as "rm" in bxInstruction_c.
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* In this class, a value greater than REG_COUNT marks this field unused.
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*/
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Bit8u opcodeRegisterOffset;
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/**
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* the ALU class this instruction belongs to
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*/
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X86AluClass aluClass;
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/**
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* the count of registers
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*/
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static const unsigned REG_COUNT = 8;
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/**
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* returns true if obj equals this object
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* the Bochs opcode is generated dynamically and thus not relevant for comparison
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*/
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bool operator==(BochsALUInstr const &obj) const
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{
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return opcode == obj.opcode &&
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reg == obj.reg &&
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opcodeRegisterOffset == obj.opcodeRegisterOffset &&
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aluClass == obj.aluClass;
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}
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/**
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* returns false if obj equals this object
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* \see operator==
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*/
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bool operator!=(BochsALUInstr const &obj) const {
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return !(*this == obj);
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}
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};
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/**
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* \var aluInstructions
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*
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* Array containing the Bochs IA-32 Integer ALU commands.
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*/
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const BochsALUInstr aluInstructions [] = {
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// Now is a great time to open Volume 2 of Intel's IA-32 documentation.
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/* --- /// UNARY OPERATIONS \\\ --- */
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// 8-bit
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{ BX_IA_INC_Eb, 0xFE, 0, BochsALUInstr::REG_COUNT + 1, ALU_RM8},
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{ BX_IA_DEC_Eb, 0xFE, 1, BochsALUInstr::REG_COUNT + 1, ALU_RM8},
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{ BX_IA_NOT_Eb, 0xF6, 2, BochsALUInstr::REG_COUNT + 1, ALU_RM8},
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{ BX_IA_NEG_Eb, 0xF6, 3, BochsALUInstr::REG_COUNT + 1, ALU_RM8},
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// 16-bit
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{ BX_IA_INC_Ew, 0xFF, 0, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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{ BX_IA_DEC_Ew, 0xFF, 1, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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{ BX_IA_NOT_Ew, 0xF7, 2, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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{ BX_IA_NEG_Ew, 0xF7, 3, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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// 32-bit
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{ BX_IA_INC_Ed, 0xFF, 0, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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{ BX_IA_DEC_Ed, 0xFF, 1, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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{ BX_IA_NOT_Ed, 0xF7, 2, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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{ BX_IA_NEG_Ed, 0xF7, 3, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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// register
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{ BX_IA_INC_RX, 0x40, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT, ALU_GENERIC},
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{ BX_IA_DEC_RX, 0x48, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT, ALU_GENERIC},
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{ BX_IA_INC_ERX, 0x40, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT, ALU_GENERIC},
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{ BX_IA_DEC_ERX, 0x48, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT, ALU_GENERIC},
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/* --- \\\ UNARY OPERATIONS /// --- */
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/* --- /// BCD ADJUSTMENT \\\ --- */
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{ BX_IA_DAA, 0x27, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_GENERIC},
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{ BX_IA_DAS, 0x2F, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_GENERIC},
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{ BX_IA_AAA, 0x37, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_GENERIC},
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{ BX_IA_AAS, 0x3F, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_GENERIC},
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{ BX_IA_AAM, 0xD4, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM8 },
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{ BX_IA_AAD, 0xD5, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM8 },
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/* --- \\\ BCD ADJUSTMENT /// --- */
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/* --- /// SHIFT OPERATIONS \\\ --- */
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// a macro to reduce copy-paste overhead
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#define SHIFTOPS(OPCODE, WD, CLASS) \
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{ BX_IA_RCL_E##WD, OPCODE, 2, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_RCR_E##WD, OPCODE, 3, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_ROL_E##WD, OPCODE, 0, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_ROR_E##WD, OPCODE, 1, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SHL_E##WD, OPCODE, 4, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SAR_E##WD, OPCODE, 7, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SHL_E##WD, OPCODE, 6, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SHR_E##WD, OPCODE, 5, BochsALUInstr::REG_COUNT + 1, CLASS }
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// first shifting by one bit
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SHIFTOPS(0xD0, b, ALU_RM8),
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SHIFTOPS(0xD1, w, ALU_RM16),
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SHIFTOPS(0xD1, d, ALU_RM32),
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// then shifting by CL bits
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SHIFTOPS(0xD2, b, ALU_RM8),
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SHIFTOPS(0xD3, w, ALU_RM16),
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SHIFTOPS(0xD3, d, ALU_RM32),
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// then shifting by a number of bits given via an immediate value
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SHIFTOPS(0xC0, b, ALU_IMM8_RM8),
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SHIFTOPS(0xC1, w, ALU_IMM8_RM16),
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SHIFTOPS(0xC1, d, ALU_IMM8_RM32),
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#undef SHIFTOPS
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// SHLD / SHRD (Note: Bochs Opcode; normally 0x0F...)
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{ BX_IA_SHLD_EwGw, 0xA4, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM16 },
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{ BX_IA_SHLD_EdGd, 0xA4, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM32 },
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{ BX_IA_SHLD_EwGw, 0xA5, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16 },
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{ BX_IA_SHLD_EdGd, 0xA5, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32 },
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{ BX_IA_SHRD_EwGw, 0xAC, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM16 },
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{ BX_IA_SHRD_EdGd, 0xAC, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM32 },
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{ BX_IA_SHRD_EwGw, 0xAD, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16 },
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{ BX_IA_SHRD_EdGd, 0xAD, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32 },
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/* --- \\\ SHIFT OPERATIONS /// --- */
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/* --- /// BINARY OPERATIONS \\\ --- */
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// register ax, immediate
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_ALIb, OPCODE8, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM8 }, \
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{ BX_IA_##IACODE##_AXIw, OPCODE16, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM16 }, \
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{ BX_IA_##IACODE##_EAXId, OPCODE16, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM32 }
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BINOPS(ADC, 0x14, 0x15),
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BINOPS(ADD, 0x04, 0x05),
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BINOPS(AND, 0x24, 0x25),
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BINOPS(CMP, 0x3C, 0x3D),
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BINOPS(OR, 0x0C, 0x0D),
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BINOPS(SBB, 0x1C, 0x1D),
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BINOPS(SUB, 0x2C, 0x2D),
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BINOPS(XOR, 0x34, 0x35),
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#undef BINOPS
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// r/m, immediate
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#define BINOPS(OPCODE, WDE, WDI, CLASS) \
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{ BX_IA_ADC_E##WDE##I##WDI, OPCODE, 2, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_ADD_E##WDE##I##WDI, OPCODE, 0, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_AND_E##WDE##I##WDI, OPCODE, 4, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_CMP_E##WDE##I##WDI, OPCODE, 7, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_OR_E##WDE##I##WDI, OPCODE, 1, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SBB_E##WDE##I##WDI, OPCODE, 3, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_SUB_E##WDE##I##WDI, OPCODE, 5, BochsALUInstr::REG_COUNT + 1, CLASS }, \
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{ BX_IA_XOR_E##WDE##I##WDI, OPCODE, 6, BochsALUInstr::REG_COUNT + 1, CLASS }
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BINOPS(0x80, b, b, ALU_IMM8_RM8),
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BINOPS(0x81, w, w, ALU_IMM16_RM16),
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BINOPS(0x81, d, d, ALU_IMM32_RM32),
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BINOPS(0x82, b, b, ALU_IMM8_RM8),
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BINOPS(0x83, w, w, ALU_IMM8_RM16),
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BINOPS(0x83, d, d, ALU_IMM8_RM32),
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#undef BINOPS
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// r/m, arbitrary register
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_EbGb, OPCODE8, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM8 }, \
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{ BX_IA_##IACODE##_EwGw, OPCODE16, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16 }, \
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{ BX_IA_##IACODE##_EdGd, OPCODE16, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32 }
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BINOPS(ADC, 0x10, 0x11),
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BINOPS(ADD, 0x00, 0x01),
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BINOPS(AND, 0x20, 0x21),
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BINOPS(CMP, 0x38, 0x39),
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BINOPS(OR, 0x08, 0x09),
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BINOPS(SBB, 0x18, 0x19),
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BINOPS(SUB, 0x28, 0x29),
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BINOPS(XOR, 0x30, 0x31),
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#undef BINOPS
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// arbitrary register, r/m
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#define BINOPS(IACODE, OPCODE8, OPCODE16) \
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{ BX_IA_##IACODE##_GbEb, OPCODE8, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM8 }, \
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{ BX_IA_##IACODE##_GwEw, OPCODE16, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16 }, \
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{ BX_IA_##IACODE##_GdEd, OPCODE16, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32 }
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BINOPS(ADC, 0x12, 0x13),
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BINOPS(ADD, 0x02, 0x03),
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BINOPS(AND, 0x22, 0x23),
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BINOPS(CMP, 0x3A, 0x3B),
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BINOPS(OR, 0x0A, 0x0B),
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BINOPS(SBB, 0x1A, 0x1B),
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BINOPS(SUB, 0x2A, 0x2B),
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BINOPS(XOR, 0x32, 0x33),
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#undef BINOPS
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// TEST instruction
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{ BX_IA_TEST_ALIb, 0xA8, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM8},
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{ BX_IA_TEST_AXIw, 0xA9, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM16},
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{ BX_IA_TEST_EAXId, 0xA9, BochsALUInstr::REG_COUNT + 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM32},
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{ BX_IA_TEST_EbIb, 0xF6, 0, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM8 },
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{ BX_IA_TEST_EbIb, 0xF6, 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM8 },
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{ BX_IA_TEST_EwIw, 0xF7, 0, BochsALUInstr::REG_COUNT + 1, ALU_IMM16_RM16 },
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{ BX_IA_TEST_EwIw, 0xF7, 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM16_RM16 },
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{ BX_IA_TEST_EdId, 0xF7, 0, BochsALUInstr::REG_COUNT + 1, ALU_IMM32_RM32 },
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{ BX_IA_TEST_EdId, 0xF7, 1, BochsALUInstr::REG_COUNT + 1, ALU_IMM32_RM32 },
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{ BX_IA_TEST_EbGb, 0x84, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM8},
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{ BX_IA_TEST_EwGw, 0x85, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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{ BX_IA_TEST_EdGd, 0x85, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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// MUL and DIV
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#define BINOPS(IACODE, OPCODE8, OPCODE16, REG) \
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{ BX_IA_##IACODE##_ALEb, OPCODE8, REG, BochsALUInstr::REG_COUNT + 1, ALU_IMM8 }, \
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{ BX_IA_##IACODE##_AXEw, OPCODE16, REG, BochsALUInstr::REG_COUNT + 1, ALU_IMM16 }, \
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{ BX_IA_##IACODE##_EAXEd, OPCODE16, REG, BochsALUInstr::REG_COUNT + 1, ALU_IMM32 }
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BINOPS(MUL, 0xF6, 0xF7, 4),
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BINOPS(IMUL, 0xF6, 0xF7, 5),
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BINOPS(DIV, 0xF6, 0xF7, 6),
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BINOPS(IDIV, 0xF6, 0xF7, 7),
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#undef BINOPS
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{ BX_IA_IMUL_GwEwIw, 0x69, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM16_RM16 },
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{ BX_IA_IMUL_GwEwIw, 0x69, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM32_RM32 },
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{ BX_IA_IMUL_GwEwIw, 0x6B, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM16 },
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{ BX_IA_IMUL_GwEwIw, 0x6B, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_IMM8_RM32 },
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// two-byte opcode, see above
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{ BX_IA_IMUL_GwEw, 0xAF, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM16},
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{ BX_IA_IMUL_GdEd, 0xAF, BochsALUInstr::REG_COUNT, BochsALUInstr::REG_COUNT + 1, ALU_RM32},
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/* --- \\\ BINARY OPERATIONS /// --- */
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};
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/**
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* \var aluInstructionsSize
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*
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* the size of aluInstructions, in bytes
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*/
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size_t const aluInstructionsSize = sizeof(aluInstructions);
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/**
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* \class BochsALUInstructions
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*
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* \brief This class handles Bochs ALU instructions.
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*
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* This class analyses a given bxInstruction_c object:
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* if it belongs to the instructions listed in
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* \a allInstr, the user can request a random
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* ALU instruction with an equivalent addressing mode.
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*/
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class BochsALUInstructions {
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public:
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/**
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* A list of Bochs instructions
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*/
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typedef std::vector<BochsALUInstr> InstrList;
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/**
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* This data structure assigns lists of instructions on their ALU equivalence
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* class.
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*
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* \see X86AluClass
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*/
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typedef std::map<X86AluClass, InstrList> EquivClassMap;
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/**
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* Creates a new BochsALUInstructions object.
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* @param initial_array initialises \a allInstr
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* @param array_size the size of initial_array
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*/
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BochsALUInstructions(const BochsALUInstr *initial_array, size_t array_size);
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/**
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* Destroys the BochsALUInstructions object.
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*/
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~BochsALUInstructions() { free(allInstr); }
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/**
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* Determines if a given Bochs instruction is an ALU instruction.
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* @param src the instruction to examine. It is stored internally
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* to be reused with \a randomEquivalent
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* @returns \c true if the given instruction is an ALU instruction,
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* \c false otherwise
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*/
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bool isALUInstruction(const bxInstruction_c *src);
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/**
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* Determines a new bxInstruction_c object with an equivalent
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* addressing mode.
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* @param result the resulting bxInstruction_c object as described above
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* @param details after completion contains details about \c result
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*/
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void randomEquivalent(bxInstruction_c &result, std::string &details) const;
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protected:
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/**
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* Convert a bxInstruction_c object into its matching BochsALUInstr object.
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* @params src the Bochs instruction to examine
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* @params dest the resulting BochsALUInstr object. Its \a aluClass field
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* is set to \c ALU_UNDEF in case no matching ALU instruction
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* could be found. In this case, all other fields of dest are invalid.
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*/
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void bochsInstrToInstrStruct(bxInstruction_c const &src, BochsALUInstr &dest) const;
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private:
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BochsALUInstr *allInstr; //<! array that contains all known ALU instructions of the object
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size_t allInstrSize; //<! the element count of the allInstr array
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BochsALUInstr lastInstr; //<! a buffer for the last generated ALU instruction
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bxInstruction_c lastOrigInstr; //!< a buffer for the last examined Bochs instruction
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EquivClassMap equivalenceClasses; //!< the object's \a EquivClassMap (see there)
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/**
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* A function to build the equivalence classes from the given instructions.
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*/
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void buildEquivalenceClasses();
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#ifdef DEBUG
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void printNestedMap(); //!< prints the \a EquivClassMap of the oject
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#endif
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};
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#endif // __L4SYS_ALUINSTR_HPP__
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