b70b6fb43a
"failstar" sounds like a name for a cruise liner from the 80s. As "*" isn't a desirable part of directory names, just name the whole thing "fail/", the core parts being stored in "fail/core/". Additionally fixing two build system dependency issues: - missing jobserver -> protomessages dependency - broken bochs -> fail dependency (add_custom_target DEPENDS only allows plain file dependencies ... cmake for the win) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@956 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
121 lines
3.6 KiB
C
121 lines
3.6 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_EXCEPTION_TYPES_H
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#define ARM_EXCEPTION_TYPES_H
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//
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// This enumerates exceptions
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//
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typedef enum armExceptNumE {
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AEN_None = 0,
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AEN_Reset = 1,
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AEN_NMI = 2,
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AEN_HardFault = 3,
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AEN_MemManage = 4,
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AEN_BusFault = 5,
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AEN_UsageFault = 6,
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AEN_SVCall = 11,
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AEN_DebugMonitor = 12,
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AEN_PendSV = 14,
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AEN_SysTick = 15,
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AEN_ExternalInt0 = 16,
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AEN_LAST = 512 // KEEP LAST: for sizing
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} armExceptNum;
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//
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// This identifies whether the passed exception is an interrupt (and whether
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// SCR.SLEEPONEXIT applies to this exception type)
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//
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#define EX_IS_INTERRUPT(_E) ((_E)>=AEN_PendSV)
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//
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// This enumerates the context of a load/store exception
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//
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typedef enum armExceptCxtE {
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AEC_None = 0,
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AEC_PushStack,
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AEC_PopStack,
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AEC_ReadVector,
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AEC_PreserveFPState
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} armExceptCxt;
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//
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// This defines permanently-enabled exceptions
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//
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#define ARM_EXCEPT_PERMANENT_ENABLE ( \
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(1 << AEN_Reset) | \
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(1 << AEN_NMI) | \
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(1 << AEN_HardFault) | \
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(1 << AEN_SVCall) | \
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(1 << AEN_PendSV) | \
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(1 << AEN_SysTick) \
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)
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//
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// Utility macros for accessing exception bitmasks
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//
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#define EX_MASK_INDEX(_N) ((_N)/32)
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#define EX_MASK_BIT(_N) ((_N)&31)
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#define EX_MASK_MASK(_N) (1<<EX_MASK_BIT(_N))
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#define EX_MASK_GET(_M, _N) ((_M[EX_MASK_INDEX(_N)] >> EX_MASK_BIT(_N)) & 1)
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#define EX_MASK_SET_1(_M, _N) _M[EX_MASK_INDEX(_N)] |= EX_MASK_MASK(_N)
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#define EX_MASK_SET_0(_M, _N) _M[EX_MASK_INDEX(_N)] &= ~EX_MASK_MASK(_N)
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#define EX_MASK_SET_V(_M, _N, _V) { \
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EX_MASK_SET_0(_M, _N); \
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_M[EX_MASK_INDEX(_N)] |= ((_V)<<EX_MASK_BIT(_N)); \
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}
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//
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// Masks for the low and high halves of interrupt registers
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//
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#define EX_INT_MASK_LO ((1<<AEN_ExternalInt0)-1)
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#define EX_INT_MASK_HI (~EX_INT_MASK_LO)
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//
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// Masks for extraction of fields from targetPC possibly specifying exception
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// return
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//
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#define EXC_RETURN_MAGIC 0xf0000000
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#define EXC_RETURN_TYPE 0x0000000f
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//
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// Masks for undefined instruction reasons
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//
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#define EXC_UNDEF_NOCP 0x00080000
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#define EXC_UNDEF_UNDEFINSTR 0x00010000
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#endif
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