b052c0494b
- The register manager is gone. It's functionality is now encapsulated in the CPU classes. - For the client, there is the ConcreteCPU class that encapsulates the access to the CPU state (including registers) and architecture details. The correspondig objects for the CPUs inside the simulator can be accessed through the SimulatorController.getCPU() function. - Listener got a new ConcreteCPU* member to filter for which CPU the events should fire. The default NULL is used as wildcard for all aviable CPUs. The events respectively got a ConcreteCPU* member to indicate which CPU really fired the event. - For the server, there is CPUArchitecture to access the architecture details. git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
60 lines
1.3 KiB
C++
60 lines
1.3 KiB
C++
#include "Gem5ArmCPU.hpp"
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namespace fail {
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regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
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{
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switch (reg->getType()) {
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case RT_GP:
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return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
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case RT_FP:
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return m_System->getThreadContext(m_Id)->readFloatReg(reg->getIndex());
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case RT_ST:
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return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
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case RT_IP:
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return getRegisterContent(getRegister(RI_IP));
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}
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// This shouldn't be reached if a valid register is passed
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return 0;
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}
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void Gem5ArmCPU::setRegisterContent(Register* reg, regdata_t value)
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{
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switch (reg->getType()) {
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case RT_GP:
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m_System->getThreadContext(m_Id)->setIntReg(reg->getIndex(), value);
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break;
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case RT_FP:
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m_System->getThreadContext(m_Id)->setFloatReg(reg->getIndex(), value);
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break;
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case RT_ST:
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return m_System->getThreadContext(m_Id)->setMiscReg(reg->getIndex(), value);
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case RT_IP:
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return setRegisterContent(getRegister(RI_IP), value);
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}
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}
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address_t Gem5ArmCPU::getInstructionPointer()
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{
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return getRegisterContent(getRegister(RI_IP));
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}
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address_t Gem5ArmCPU::getStackPointer()
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{
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return getRegisterContent(getRegister(RI_SP));
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}
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address_t Gem5ArmCPU::getLinkRegister()
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{
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return getRegisterContent(getRegister(RI_LR));
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}
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} // end-of-namespace: fail
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