b41eec3f65
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
73 lines
3.4 KiB
Python
73 lines
3.4 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Andreas Hansson
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from MemObject import MemObject
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from m5.params import *
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class BaseBus(MemObject):
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type = 'BaseBus'
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abstract = True
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slave = VectorSlavePort("vector port for connecting masters")
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master = VectorMasterPort("vector port for connecting slaves")
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clock = Param.Clock("1GHz", "bus clock speed")
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header_cycles = Param.Int(1, "cycles of overhead per transaction")
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width = Param.Int(64, "bus width (bytes)")
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block_size = Param.Int(64, "The default block size if not set by " \
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"any connected module")
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# The default port can be left unconnected, or be used to connect
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# a default slave port
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default = MasterPort("Port for connecting an optional default slave")
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# The default port can be used unconditionally, or based on
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# address range, in which case it may overlap with other
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# ports. The default range is always checked first, thus creating
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# a two-level hierarchical lookup. This is useful e.g. for the PCI
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# bus configuration.
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use_default_range = Param.Bool(False, "Perform address mapping for " \
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"the default port")
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class NoncoherentBus(BaseBus):
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type = 'NoncoherentBus'
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class CoherentBus(BaseBus):
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type = 'CoherentBus'
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