9a47d75f9a
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1307 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
247 lines
7.7 KiB
C++
247 lines
7.7 KiB
C++
#ifndef __BOCHS_REGISTER_HPP__
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#define __BOCHS_REGISTER_HPP__
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#include "../Register.hpp"
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#include "../../../bochs/bochs.h"
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#include <iostream>
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#include <cassert>
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namespace sal {
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/**
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* \class BochsRegister
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* Bochs-specific implementation of x86 registers.
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*/
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class BochsRegister : public Register
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{
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protected:
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regdata_t* m_pData;
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public:
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/**
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* Constructs a new register object.
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* @param id the global unique id
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* @param width width of the register (8, 16, 32 or 64 bit should
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* suffice)
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* @param link pointer to bochs interal register memory
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* @param t type of the register
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*/
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BochsRegister(unsigned int id, regwidth_t width, regdata_t* link, RegisterType t)
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: Register(id, t, width), m_pData(link) { }
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/**
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* Retrieves the data of the register.
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* @return the current register data
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*/
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regdata_t getData() { return (*m_pData); }
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/**
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* Sets the content of the register.
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* @param data the new register data to be written
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*/
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void setData(regdata_t data) { *m_pData = data; }
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};
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/**
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* \class BxGPReg
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* Bochs-specific implementation of x86 general purpose (GP) registers.
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*/
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class BxGPReg : public BochsRegister
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{
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public:
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/**
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* Constructs a new general purpose register.
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* @param id the global unique id
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* @param width width of the register (8, 16, 32 or 64 bit should
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* suffice)
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* @param link pointer to bochs interal register memory
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*/
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BxGPReg(unsigned int id, regwidth_t width, regdata_t* link)
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: BochsRegister(id, width, link, RT_GP) { }
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};
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/**
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* \enum GPRegisterId
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* Symbolic identifier to access Bochs' general purpose register
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* (within the corresponding GP set), e.g.
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* \code
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* // Print %eax register data:
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* BochsController bc(...);
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* cout << bc.getRegisterManager().getSetOfType(RT_GP)
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* .getRegister(RID_EAX)->getData();
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* \endcode
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*/
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enum GPRegisterId
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{
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#if BX_SUPPORT_X86_64 // 64 bit register id's:
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RID_RAX = 0, RID_RCX, RID_RDX, RID_RBX, RID_RSP, RID_RBP, RID_RSI, RID_RDI,
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RID_R8, RID_R9, RID_R10, RID_R11, RID_R12, RID_R13, RID_R14, RID_R15,
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#else // 32 bit register id's:
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RID_EAX = 0, RID_ECX, RID_EDX, RID_EBX, RID_ESP, RID_EBP, RID_ESI, RID_EDI,
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#endif
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RID_CAX = 0, RID_CCX, RID_CDX, RID_CBX, RID_CSP, RID_CBP, RID_CSI, RID_CDI,
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RID_LAST_GP_ID
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};
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/**
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* \enum PCRegisterId
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* Symbolic identifier to access Bochs' program counter register.
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*/
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enum PCRegisterId { RID_PC = RID_LAST_GP_ID, RID_LAST_PC_ID };
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/**
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* \enum FlagsRegisterId
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* Symbolic identifier to access Bochs' flags register.
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*/
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enum FlagsRegisterId { RID_FLAGS = RID_LAST_PC_ID };
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/**
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* \class BxPCReg
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* Bochs-specific implementation of the x86 program counter register.
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*/
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class BxPCReg : public BochsRegister
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{
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public:
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/**
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* Constructs a new program counter register.
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* @param id the global unique id
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* @param width width of the register (8, 16, 32 or 64 bit should
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* suffice)
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* @param link pointer to bochs internal register memory
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*/
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BxPCReg(unsigned int id, regwidth_t width, regdata_t* link)
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: BochsRegister(id, width, link, RT_PC) { }
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};
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/**
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* \class BxFlagsReg
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* Bochs-specific implementation of the FLAGS status register.
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*/
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class BxFlagsReg : public BochsRegister
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{
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public:
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/**
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* Constructs a new FLAGS status register. The refenced FLAGS are
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* allocated as follows:
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* --------------------------------------------------
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* 31|30|29|28| 27|26|25|24| 23|22|21|20| 19|18|17|16
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* ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
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* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0|ID|VP| VF|AC|VM|RF
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*
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* 15|14|13|12| 11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
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* ==|==|=====| ==|==|==|==| ==|==|==|==| ==|==|==|==
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* 0|NT| IOPL| OF|DF|IF|TF| SF|ZF| 0|AF| 0|PF| 1|CF
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* --------------------------------------------------
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* @param id the global unique id
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* @param link pointer to bochs internal register memory
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*/
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BxFlagsReg(unsigned int id, regdata_t* link)
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: BochsRegister(id, 32, link, RT_ST) { }
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/**
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* Returns \c true if the corresponding flag is set, or \c false
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* otherwise.
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*/
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bool getCarryFlag() const { return (BX_CPU(0)->get_CF()); }
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bool getParityFlag() const { return (BX_CPU(0)->get_PF()); }
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bool getZeroFlag() const { return (BX_CPU(0)->get_ZF()); }
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bool getSignFlag() const { return (BX_CPU(0)->get_SF()); }
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bool getOverflowFlag() const { return (BX_CPU(0)->get_OF()); }
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bool getTrapFlag() const { return (BX_CPU(0)->get_TF()); }
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bool getInterruptFlag() const { return (BX_CPU(0)->get_IF()); }
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bool getDirectionFlag() const { return (BX_CPU(0)->get_DF()); }
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unsigned getIOPrivilegeLevel() const { return (BX_CPU(0)->get_IOPL()); }
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bool getNestedTaskFlag() const { return (BX_CPU(0)->get_NT()); }
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bool getResumeFlag() const { return (BX_CPU(0)->get_RF()); }
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bool getVMFlag() const { return (BX_CPU(0)->get_VM()); }
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bool getAlignmentCheckFlag() const { return (BX_CPU(0)->get_AC()); }
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bool getVInterruptFlag() const { return (BX_CPU(0)->get_VIF()); }
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bool getVInterruptPendingFlag() const { return (BX_CPU(0)->get_VIP()); }
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bool getIdentificationFlag() const { return (BX_CPU(0)->get_ID()); }
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/**
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* Sets/resets various status FLAGS.
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*/
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void setCarryFlag(bool bit) { BX_CPU(0)->set_CF(bit); }
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void setParityFlag(bool bit) { BX_CPU(0)->set_PF(bit); }
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void setZeroFlag(bool bit) { BX_CPU(0)->set_ZF(bit); }
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void setSignFlag(bool bit) { BX_CPU(0)->set_SF(bit); }
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void setOverflowFlag(bool bit) { BX_CPU(0)->set_OF(bit); }
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void setTrapFlag(bool bit) { BX_CPU(0)->set_TF(bit); }
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void setInterruptFlag(bool bit) { BX_CPU(0)->set_IF(bit); }
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void setDirectionFlag(bool bit) { BX_CPU(0)->set_DF(bit); }
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void setIOPrivilegeLevel(unsigned lvl) { BX_CPU(0)->set_IOPL(lvl); }
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void setNestedTaskFlag(bool bit) { BX_CPU(0)->set_NT(bit); }
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void setResumeFlag(bool bit) { BX_CPU(0)->set_RF(bit); }
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void setVMFlag(bool bit) { BX_CPU(0)->set_VM(bit); }
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void setAlignmentCheckFlag(bool bit) { BX_CPU(0)->set_AC(bit); }
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void setVInterruptFlag(bool bit) { BX_CPU(0)->set_VIF(bit); }
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void setVInterruptPendingFlag(bool bit) { BX_CPU(0)->set_VIP(bit); }
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void setIdentificationFlag(bool bit) { BX_CPU(0)->set_ID(bit); }
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/**
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* Sets the content of the status register.
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* @param data the new register data to be written; note that only the
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* 32 lower bits are used (bits 32-63 are ignored in 64 bit mode)
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*/
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void setData(regdata_t data)
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{
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#ifdef BX_SUPPORT_X86_64
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// We are in 64 bit mode: Just assign the lower 32 bits!
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(*m_pData) = ((*m_pData) & 0xFFFFFFFF00000000ULL) |
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(data & 0xFFFFFFFFULL);
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#else
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*m_pData = data;
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#endif
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}
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};
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/**
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* \class BochsRegister
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* Bochs-specific implementation of the RegisterManager.
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*/
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class BochsRegisterManager : public RegisterManager
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{
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public:
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/**
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* Returns the current instruction pointer.
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* @return the current eip
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*/
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address_t getInstructionPointer()
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{
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return (static_cast<address_t>(
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getSetOfType(RT_PC)->first()->getData()
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));
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}
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/**
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* Retruns the top address of the stack.
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* @return the starting address of the stack
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*/
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address_t getStackPointer()
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{
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#if BX_SUPPORT_X86_64
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return (static_cast<address_t>(getRegister(RID_RSP)->getData()));
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#else
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return (static_cast<address_t>(getRegister(RID_ESP)->getData()));
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#endif
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}
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/**
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* Retrieves the base ptr (holding the address of the
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* current stack frame).
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* @return the base pointer
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*/
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address_t getBasePointer()
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{
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#if BX_SUPPORT_X86_64
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return (static_cast<address_t>(getRegister(RID_RBP)->getData()));
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#else
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return (static_cast<address_t>(getRegister(RID_EBP)->getData()));
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#endif
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}
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};
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} // end-of-namespace: sal
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#endif /* __BOCHS_REGISTER_HPP__ */
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