96bc39c05d
The T32 can simulate bare instruction sets without periphery. For the Cortex-M3 we have complete NVIC model including Systick Timer. Currently a simple CiAO can run on the simulator. TODO: - Let memlogger log all memory accesses. - Interact with FailT32 for a complete simulation/FI
45 lines
1.2 KiB
Plaintext
45 lines
1.2 KiB
Plaintext
width 9. 7.
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base d:20000
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group.long 0--3 "Data1 (Simple Parallel port, available in Portanalyzer)"
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line.long 0 "Data1"
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group.long 4--7 "Data2 (Simple Parallel port)"
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line.long 0 "Data2"
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group.long 8--0x0b "Data3 (Parallel port, shared data)"
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line.long 0 "Data3"
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group.long 100--0x10b "Data4 (Relocatable Parallel port)"
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line.long 0 "Data4"
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group.byte 0x0c--0x0c "Data5 (Parallel port connected to FILE I/O)"
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line.byte 0 "Data5"
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group.byte 0x0d--0x0d "Terminal1 (Serial I/O simulation to Terminal I/O)"
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line.byte 0 "DATA"
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group.byte 0x0e--0x0e
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line.byte 0 "STAT"
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bitfld 0 7 "TXIE ,TX Interrupt Enable" "no,yes"
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bitfld 0 6 " RXIE ,RX Interrupt Enable" "no,yes"
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bitfld 0 4 " TWAV ,Terminal Window Available" "yes,no"
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bitfld 0 1 " TXR ,TX Ready" "no,yes"
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bitfld 0 0 " RXR ,RX Ready" "no,yes"
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group.long 0x200--0x20f "Ram1 (Shared memory)"
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line.long 0 "00"
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line.long 4 "04"
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line.long 8 "08"
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line.long 0c "0c"
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group.long 0x10--0x13 "Timer1 (Incrementing each 100 clockticks)"
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line.long 0 "Timer1"
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group.long 0x14--0x17 "Timer2 (Incrementing on each Port #0xf0 rising edge)"
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line.long 0 "Timer2"
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group.long 0x18--0x1b "Timer3 (Decrementing each clockticks after activation)"
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line.long 0 "Timer3"
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