96bc39c05d
The T32 can simulate bare instruction sets without periphery. For the Cortex-M3 we have complete NVIC model including Systick Timer. Currently a simple CiAO can run on the simulator. TODO: - Let memlogger log all memory accesses. - Interact with FailT32 for a complete simulation/FI
264 lines
6.8 KiB
C
264 lines
6.8 KiB
C
#include "nvic.h"
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/*************** Irq x Set Enable Register ***************/
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int IRQSETENR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQSETENR_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus,®);
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for (i=0;i<32;i++)
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{
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if (reg & (1<<i)) ChangeEnable(arrayidx+i,1);
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}
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Interrupt(processor,IntCtrl,0);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Clear Enable Register ***************/
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int IRQCLRENR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQCLRENR_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus,®);
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for (i=0;i<32;i++)
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{
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if (reg & (1<<i)) ChangeEnable(arrayidx+i,0);
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}
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Interrupt(processor,IntCtrl,0);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Set Pending Register ***************/
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int IRQSETPER_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQSETPER_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int wakeUpEvent = 0;
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int i;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus,®);
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for (i=0;i<32;i++)
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{
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if (reg & (1<<i)) ChangePending(arrayidx+i,1);
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}
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Interrupt(processor,IntCtrl,wakeUpEvent);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Clear Pending Register ***************/
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int IRQCLRPER_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQCLRPER_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int wakeUpEvent = 0;
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int i;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus,®);
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for (i=0;i<32;i++)
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{
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if (reg & (1<<i)) ChangePending(arrayidx+i,0);
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}
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Interrupt(processor,IntCtrl,wakeUpEvent);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Priority Register ***************/
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int IRQPR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQPR_OFFSET) >> 2;
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int arrayidx = (idx << 2) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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for (i=0;i<4;i++) reg |= IntCtrl->IrqPriority[arrayidx+i] << (i << 3);
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BusRead(&cbs->x.bus,®);
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for (i=0;i<4;i++) IntCtrl->IrqPriority[arrayidx+i] = (unsigned char)(reg >> (i << 3));
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Set Enable Register ***************/
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int IRQSETENR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQSETENR_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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if (arrayidx<(7 * 32))
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{
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for (i=0;i<32;i++) reg |= (IntCtrl->IrqEnable[arrayidx+i])?(1<<i):(0);
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}
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else
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{
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for (i=0;i<16;i++) reg |= (IntCtrl->IrqEnable[arrayidx+i])?(1<<i):(0);
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}
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Clear Enable Register ***************/
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int IRQCLRENR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQCLRENR_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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if (arrayidx<(7 * 32))
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{
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for (i=0;i<32;i++) reg |= (IntCtrl->IrqEnable[arrayidx+i])?(1<<i):(0);
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}
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else
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{
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for (i=0;i<16;i++) reg |= (IntCtrl->IrqEnable[arrayidx+i])?(1<<i):(0);
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}
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Set Pending Register ***************/
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int IRQSETPER_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQSETPER_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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if (arrayidx<(7 * 32))
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{
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for (i=0;i<32;i++) reg |= (IntCtrl->IrqPending[arrayidx+i])?(1<<i):(0);
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}
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else
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{
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for (i=0;i<16;i++) reg |= (IntCtrl->IrqPending[arrayidx+i])?(1<<i):(0);
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}
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Clear Pending Register ***************/
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int IRQCLRPER_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQCLRPER_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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if (arrayidx<(7 * 32))
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{
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for (i=0;i<32;i++) reg |= (IntCtrl->IrqPending[arrayidx+i])?(1<<i):(0);
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}
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else
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{
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for (i=0;i<16;i++) reg |= (IntCtrl->IrqPending[arrayidx+i])?(1<<i):(0);
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}
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Active Bit Register ***************/
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int IRQABR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQABR_OFFSET) >> 2;
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int arrayidx = (idx << 5) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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if (arrayidx<(7 * 32))
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{
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for (i=0;i<32;i++) reg |= (IntCtrl->IrqActive[arrayidx+i])?(1<<i):(0);
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}
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else
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{
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for (i=0;i<16;i++) reg |= (IntCtrl->IrqActive[arrayidx+i])?(1<<i):(0);
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}
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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/*************** Irq x Priority Register ***************/
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int IRQPR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = ((cbs->x.bus.address & ~0x3) - IntCtrl->baseaddress - IRQPR_OFFSET) >> 2;
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int arrayidx = (idx << 2) + 16;
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simulWord32 reg = 0;
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int i;
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cbs->x.bus.clocks = 1;
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for (i=0;i<4;i++) reg |= ((simulWord32)((unsigned char)IntCtrl->IrqPriority[arrayidx+i])) << (i << 3);
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BusWrite(&cbs->x.bus,®);
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return SIMUL_MEMORY_OK;
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}
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