96bc39c05d
The T32 can simulate bare instruction sets without periphery. For the Cortex-M3 we have complete NVIC model including Systick Timer. Currently a simple CiAO can run on the simulator. TODO: - Let memlogger log all memory accesses. - Interact with FailT32 for a complete simulation/FI
413 lines
20 KiB
C
413 lines
20 KiB
C
//#pragma warning (disable : 4100)
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#include "simul.h"
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/* Definitions */
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#define BASE_ADDRESS 0xE000E000 /* base address of controller */
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#define CMD_OFFSET 0x0000 /* Commands from ARM Simulator */
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#define ICTR_OFFSET 0x0004 /* Interrupt Control Type Register */
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#define STCSR_OFFSET 0x0010 /* SysTick Control and Status Register */
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#define STRVR_OFFSET 0x0014 /* SysTick Reload Value Register */
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#define STCVR_OFFSET 0x0018 /* SysTick Current Value Register */
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#define STCLVR_OFFSET 0x001C /* SysTick Calibration Value Register */
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#define IRQSETENR_OFFSET 0x0100 /* Irq x Set Enable Register */
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#define IRQCLRENR_OFFSET 0x0180 /* Irq x Clear Enable Register */
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#define IRQSETPER_OFFSET 0x0200 /* Irq x Set Pending Register */
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#define IRQCLRPER_OFFSET 0x0280 /* Irq x Clear Pending Register */
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#define IRQABR_OFFSET 0x0300 /* Irq x Active Bit Register */
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#define IRQPR_OFFSET 0x0400 /* Irq x Priority Register */
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#define CPUIDR_OFFSET 0x0D00 /* CPUID Base Register */
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#define ICSR_OFFSET 0x0D04 /* Interrupt Control State Register */
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#define VTOR_OFFSET 0x0D08 /* Vector Table Offset Register */
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#define AIRCR_OFFSET 0x0D0C /* Application Interrupt/Reset Control Register */
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#define SCR_OFFSET 0x0D10 /* System Control Register */
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#define CCR_OFFSET 0x0D14 /* Configuration Control Register */
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#define SHPR_OFFSET 0x0D18 /* System Handlers x Priority Register */
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#define SHCSR_OFFSET 0x0D24 /* System Handler Control and State Register */
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#define CFSR_OFFSET 0x0D28 /* Configurable Fault Status Register */
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#define HFSR_OFFSET 0x0D2C /* Hard Fault Status Register */
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#define DFSR_OFFSET 0x0D30 /* Debug Fault Status Register */
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#define MMAR_OFFSET 0x0D34 /* Memory Manage Address Register */
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#define BFAR_OFFSET 0x0D38 /* Bus Fault Address Register */
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#define AFSR_OFFSET 0x0D3C /* Auxiliary Fault Status Register */
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#define PFR0_OFFSET 0x0D40 /* Processor Feature Register 0 */
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#define PFR1_OFFSET 0x0D44 /* Processor Feature Register 1 */
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#define DFR0_OFFSET 0x0D48 /* Debug Feature Register 0 */
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#define AFR0_OFFSET 0x0D4C /* Auxiliary Feature Register 0 */
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#define MMFR0_OFFSET 0x0D50 /* Memory Model Feature Register 0 */
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#define MMFR1_OFFSET 0x0D54 /* Memory Model Feature Register 1 */
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#define MMFR2_OFFSET 0x0D58 /* Memory Model Feature Register 2 */
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#define MMFR3_OFFSET 0x0D5C /* Memory Model Feature Register 3 */
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#define ISAR0_OFFSET 0x0D60 /* ISA Feature Register 0 */
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#define ISAR1_OFFSET 0x0D64 /* ISA Feature Register 1 */
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#define ISAR2_OFFSET 0x0D68 /* ISA Feature Register 2 */
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#define ISAR3_OFFSET 0x0D6C /* ISA Feature Register 3 */
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#define ISAR4_OFFSET 0x0D70 /* ISA Feature Register 4 */
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#define STIR_OFFSET 0x0F00 /* Software Trigger Interrupt Register */
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#define PID4_OFFSET 0x0FD0 /* Peripheral Identification Register 4 */
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#define PID5_OFFSET 0x0FD4 /* Peripheral Identification Register 5 */
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#define PID6_OFFSET 0x0FD8 /* Peripheral Identification Register 6 */
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#define PID7_OFFSET 0x0FDC /* Peripheral Identification Register 7 */
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#define PID0_OFFSET 0x0FE0 /* Peripheral Identification Register 0 */
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#define PID1_OFFSET 0x0FE4 /* Peripheral Identification Register 1 */
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#define PID2_OFFSET 0x0FE8 /* Peripheral Identification Register 2 */
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#define PID3_OFFSET 0x0FEC /* Peripheral Identification Register 3 */
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#define CID0_OFFSET 0x0FF0 /* Component Identification Register 0 */
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#define CID1_OFFSET 0x0FF4 /* Component Identification Register 1 */
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#define CID2_OFFSET 0x0FF8 /* Component Identification Register 2 */
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#define CID3_OFFSET 0x0FFC /* Component Identification Register 3 */
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#define DHCSR_OFFSET 0x0DF0 /* Debug Halting Control and Status Register */
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#ifdef _DEBUG
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#define GPIO_OFFSET 0x6000340C
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#endif
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#define CMD_SIZE 4 /* Commands Register */
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#define ICTR_SIZE 4 /* Interrupt Control Type Register */
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#define STCSR_SIZE 4 /* SysTick Control and Status Register */
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#define STRVR_SIZE 4 /* SysTick Reload Value Register */
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#define STCVR_SIZE 4 /* SysTick Current Value Register */
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#define STCLVR_SIZE 4 /* SysTick Calibration Value Register */
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#define IRQSETENR_SIZE 32 /* Irq x Set Enable Register */
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#define IRQCLRENR_SIZE 32 /* Irq x Clear Enable Register */
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#define IRQSETPER_SIZE 32 /* Irq x Set Pending Register */
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#define IRQCLRPER_SIZE 32 /* Irq x Clear Pending Register */
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#define IRQABR_SIZE 32 /* Irq x Active Bit Register */
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#define IRQPR_SIZE 240 /* Irq x Priority Register */
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#define CPUIDR_SIZE 4 /* CPUID Base Register */
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#define ICSR_SIZE 4 /* Interrupt Control State Register */
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#define VTOR_SIZE 4 /* Vector Table Offset Register */
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#define AIRCR_SIZE 4 /* Application Interrupt/Reset Control Register */
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#define SCR_SIZE 4 /* System Control Register */
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#define CCR_SIZE 4 /* Configuration Control Register */
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#define SHPR_SIZE 12 /* System Handlers x Priority Register */
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#define SHCSR_SIZE 4 /* System Handler Control and State Register */
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#define CFSR_SIZE 4 /* Configurable Fault Status Register */
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#define HFSR_SIZE 4 /* Hard Fault Status Register */
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#define DFSR_SIZE 4 /* Debug Fault Status Register */
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#define MMAR_SIZE 4 /* Memory Manage Address Register */
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#define BFAR_SIZE 4 /* Bus Fault Address Register */
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#define AFSR_SIZE 4 /* Auxiliary Fault Status Register */
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#define PFR0_SIZE 4 /* Processor Feature Register 0 */
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#define PFR1_SIZE 4 /* Processor Feature Register 1 */
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#define DFR0_SIZE 4 /* Debug Feature Register 0 */
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#define AFR0_SIZE 4 /* Auxiliary Feature Register 0 */
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#define MMFR0_SIZE 4 /* Memory Model Feature Register 0 */
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#define MMFR1_SIZE 4 /* Memory Model Feature Register 1 */
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#define MMFR2_SIZE 4 /* Memory Model Feature Register 2 */
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#define MMFR3_SIZE 4 /* Memory Model Feature Register 3 */
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#define ISAR0_SIZE 4 /* ISA Feature Register 0 */
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#define ISAR1_SIZE 4 /* ISA Feature Register 1 */
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#define ISAR2_SIZE 4 /* ISA Feature Register 2 */
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#define ISAR3_SIZE 4 /* ISA Feature Register 3 */
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#define ISAR4_SIZE 4 /* ISA Feature Register 4 */
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#define STIR_SIZE 4 /* Software Trigger Interrupt Register */
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#define PID4_SIZE 4 /* Peripheral Identification Register 4 */
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#define PID5_SIZE 4 /* Peripheral Identification Register 5 */
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#define PID6_SIZE 4 /* Peripheral Identification Register 6 */
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#define PID7_SIZE 4 /* Peripheral Identification Register 7 */
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#define PID0_SIZE 4 /* Peripheral Identification Register 0 */
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#define PID1_SIZE 4 /* Peripheral Identification Register 1 */
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#define PID2_SIZE 4 /* Peripheral Identification Register 2 */
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#define PID3_SIZE 4 /* Peripheral Identification Register 3 */
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#define CID0_SIZE 4 /* Component Identification Register 0 */
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#define CID1_SIZE 4 /* Component Identification Register 1 */
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#define CID2_SIZE 4 /* Component Identification Register 2 */
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#define CID3_SIZE 4 /* Component Identification Register 3 */
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#define DHCSR_SIZE 4 /* Debug Halting Control and Status Register */
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#ifdef _DEBUG
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#define GPIO_SIZE 12
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#endif
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int VH_Display_KKEY_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CMD_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int ICTR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STRVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STCVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STCLVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQSETENR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQCLRENR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQSETPER_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQCLRPER_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQABR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQPR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CPUIDR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int ICSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int VTOR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int AIRCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SHPR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SHCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int HFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int DFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int MMAR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int BFAR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int AFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int Feature_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int ID_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int DHCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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#ifdef _DEBUG
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int GPIO_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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#endif
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int CMD_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STRVR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STCVR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQSETENR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQCLRENR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQSETPER_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQCLRPER_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int IRQPR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CPUIDR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int ICSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int VTOR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int AIRCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SHPR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int SHCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int CFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int HFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int DFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int MMAR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int BFAR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int AFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int STIR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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int DHCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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#ifdef _DEBUG
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int GPIO_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr dummy);
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#endif
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int BusRead(simulBusCallbackStruct * bus, simulWord32 * reg);
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int BusWrite(simulBusCallbackStruct * bus, simulWord32 * reg);
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void Interrupt(simulProcessor processor, simulPtr _private,int wakeUpEvent);
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void RequestReset(simulProcessor processor);
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#define ChangePending(isrnum,value) {\
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int _changePendingValue = !!(value);\
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if (!IntCtrl->IrqPending[isrnum] && (_changePendingValue))\
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{\
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if (IntCtrl->regs.scr & REG_SCR_SEVONPEND) WakeUpFromWFE(processor,IntCtrl);\
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}\
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\
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IntCtrl->IrqPending[isrnum] = !!(value);\
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}
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#define ChangeEnable(isrnum,value) {\
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IntCtrl->IrqEnable[isrnum] = !!(value);\
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}
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#define ChangeActive(isrnum,value) {\
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IntCtrl->IrqActive[isrnum] = !!(value);\
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}
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typedef struct {
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simulWord cmd;
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simulWord ictr,stcsr,strvr,stcvr,stclvr/*,irqsetenr[8],irqclrenr[8],irqsetper[8],irqclrper[8],irqabr[8],irqpr[8]*/;
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simulWord cpuidr,icsr,vtor,aircr,scr,ccr/*,shpr[3]*/,shcsr,cfsr,hfsr,dfsr,mmar,bfar,afsr,pfr0,pfr1,dfr0,afr0,mmfr0;
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simulWord mmfr1,mmfr2,mmfr3,isar0,isar1,isar2,isar3,isar4,stir,pid4,pid5,pid6,pid7,pid0,pid1,pid2,pid3,cid0,cid1,cid2,cid3,dhcsr;
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simulWord gpio;
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} NVIC_Regs;
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typedef struct {
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int IrqNum;
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int IrqPrio;
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} NVIC_IrqStack;
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typedef struct {
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int bustype;
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simulWord baseaddress;
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NVIC_Regs regs;
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int IrqPriority[256];
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int IrqActive[256];
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int IrqEnable[256];
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int IrqPending[256];
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int CurrentIrqNum;
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int ExternalIrqPortsFirst;
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int ExternalIrqPortsCount;
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int timerrun;
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void *timer;
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} IntController;
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void WakeUpFromWFE(simulProcessor processor, IntController * IntCtrl);
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#define REG_ICSR_NMIPENDSET 0x80000000
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#define REG_ICSR_PENDSVSET 0x10000000
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#define REG_ICSR_PENDSVCLR 0x08000000
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#define REG_ICSR_PENDSTSET 0x04000000
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#define REG_ICSR_PENDSTCLR 0x02000000
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#define REG_HFSR_DEBUGEVT 0x80000000
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#define REG_HFSR_FORCED 0x40000000
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#define REG_HFSR_VECTTBL 0x00000002
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#define REG_HFSR_MASK (\
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REG_HFSR_DEBUGEVT |\
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REG_HFSR_FORCED |\
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REG_HFSR_VECTTBL\
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)
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#define REG_SHCSR_MEMFAULTENA 0x00010000
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#define REG_SHCSR_BUSFAULTENA 0x00020000
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#define REG_SHCSR_USGFAULTENA 0x00040000
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#define REG_SHCSR_SVCALLPENDED 0x8000
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#define REG_SHCSR_BUSFAULTPENDED 0x4000
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#define REG_SHCSR_MEMFAULTPENDED 0x2000
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#define REG_SHCSR_USGFAULTPENDED 0x1000
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#define REG_SHCSR_SYSTICKACT 0x800
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#define REG_SHCSR_PENDSVACT 0x400
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#define REG_SHCSR_MONITORACT 0x100
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#define REG_SHCSR_SVCALLACT 0x080
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#define REG_SHCSR_USGFAULTACT 0x008
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#define REG_SHCSR_BUSFAULTACT 0x002
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#define REG_SHCSR_MEMFAULTACT 0x001
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#define REG_CFSR_MMFSR_MMARVALID 0x00000080
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#define REG_CFSR_MMFSR_MLSPERR 0x00000020
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#define REG_CFSR_MMFSR_MSTKERR 0x00000010
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#define REG_CFSR_MMFSR_MUNSTKERR 0x00000008
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#define REG_CFSR_MMFSR_DACCVIOL 0x00000002
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#define REG_CFSR_MMFSR_IACCVIOL 0x00000001
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#define REG_CFSR_MMFSR_MASK (\
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REG_CFSR_MMFSR_MMARVALID |\
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REG_CFSR_MMFSR_MLSPERR |\
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REG_CFSR_MMFSR_MSTKERR |\
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REG_CFSR_MMFSR_MUNSTKERR |\
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REG_CFSR_MMFSR_DACCVIOL |\
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REG_CFSR_MMFSR_IACCVIOL\
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)
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#define REG_CFSR_BFSR_BFARVALID (0x00000080<<8)
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#define REG_CFSR_BFSR_LSPERR (0x00000020<<8)
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#define REG_CFSR_BFSR_STKERR (0x00000010<<8)
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#define REG_CFSR_BFSR_UNSTKERR (0x00000008<<8)
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#define REG_CFSR_BFSR_IMPRECISERR (0x00000004<<8)
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#define REG_CFSR_BFSR_PRECISERR (0x00000002<<8)
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#define REG_CFSR_BFSR_IBUSERR (0x00000001<<8)
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#define REG_CFSR_BFSR_MASK (\
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REG_CFSR_BFSR_BFARVALID |\
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REG_CFSR_BFSR_LSPERR |\
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REG_CFSR_BFSR_STKERR |\
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REG_CFSR_BFSR_UNSTKERR |\
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REG_CFSR_BFSR_IMPRECISERR |\
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REG_CFSR_BFSR_PRECISERR |\
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REG_CFSR_BFSR_IBUSERR \
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)
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#define REG_CFSR_UFSR_DIVBYZERO (0x00000200<<16)
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#define REG_CFSR_UFSR_UNALIGNED (0x00000100<<16)
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#define REG_CFSR_UFSR_NOCP (0x00000008<<16)
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#define REG_CFSR_UFSR_INVPC (0x00000004<<16)
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#define REG_CFSR_UFSR_INVSTATE (0x00000002<<16)
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#define REG_CFSR_UFSR_UNDEFINSTR (0x00000001<<16)
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#define REG_CFSR_UFSR_MASK (\
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REG_CFSR_UFSR_DIVBYZERO |\
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REG_CFSR_UFSR_UNALIGNED |\
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REG_CFSR_UFSR_NOCP |\
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REG_CFSR_UFSR_INVPC |\
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REG_CFSR_UFSR_INVSTATE |\
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REG_CFSR_UFSR_UNDEFINSTR \
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)
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#define REG_CFSR_MASK (\
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REG_CFSR_MMFSR_MASK |\
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REG_CFSR_BFSR_MASK |\
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REG_CFSR_UFSR_MASK \
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)
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#define REG_DFSR_EXTERNAL 0x00000010
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#define REG_DFSR_VCATCH 0x00000008
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#define REG_DFSR_DWTTRAP 0x00000004
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#define REG_DFSR_BKPT 0x00000002
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#define REG_DFSR_HALTED 0x00000001
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#define REG_DFSR_MASK (\
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REG_DFSR_BKPT |\
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REG_DFSR_DWTTRAP |\
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REG_DFSR_EXTERNAL |\
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REG_DFSR_HALTED |\
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REG_DFSR_VCATCH\
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)
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#define REG_STCSR_COUNTFLAG 0x00010000
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#define REG_STCSR_CLKSOURCE 0x00000004
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#define REG_STCSR_TICKINT 0x00000002
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#define REG_STCSR_ENABLE 0x00000001
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#define REG_STCLVR_NOREF 0x80000000
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#define REG_STCLVR_SKEW 0x40000000
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#define REG_STCLVR_TENMS 0x00FFFFFF
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#define REG_AFSR_MASK 0xFFFFFFFF
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#define REG_SCR_SEVONPEND 0x00000010
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#define REG_SCR_SLEEPONEXIT 0x00000002
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#define REG_SCR_MASK (\
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REG_SCR_SEVONPEND |\
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REG_SCR_SLEEPONEXIT\
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)
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#define REG_DHCSR_S_SLEEP 0x00040000
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#define REG_CCR_STKALIGN 0x00000200
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#define REG_CCR_BFHFNMIGN 0x00000100
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#define REG_CCR_DIV_0_TRP 0x00000010
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|
#define REG_CCR_UNALIGN_TRP 0x00000008
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|
#define REG_CCR_USERSETMPEND 0x00000002
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|
#define REG_CCR_NONBASETHRDENA 0x00000001
|
|
|
|
#define REG_CCR_MASK 0x0000031B
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|
|
|
#define REG_AIRCR_ENDIANNESS 0x00008000
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|
#define REG_AIRCR_PRIGROUP 0x00000700
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|
#define REG_AIRCR_SYSRESETREQ 0x00000004
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|
#define REG_AIRCR_VECTCLRACTIVE 0x00000002
|
|
#define REG_AIRCR_VECTRESET 0x00000001
|
|
|
|
#define REG_AIRCR_MASK (\
|
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REG_AIRCR_ENDIANNESS |\
|
|
REG_AIRCR_PRIGROUP |\
|
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REG_AIRCR_SYSRESETREQ |\
|
|
REG_AIRCR_VECTCLRACTIVE |\
|
|
REG_AIRCR_VECTRESET\
|
|
)
|
|
|
|
#define IRQNUM_RESET 1
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|
#define IRQNUM_NMI 2
|
|
#define IRQNUM_HARDFAULT 3
|
|
#define IRQNUM_MEMFAULT 4
|
|
#define IRQNUM_BUSFAULT 5
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|
#define IRQNUM_USAGEFAULT 6
|
|
#define IRQNUM_SVCALL 11
|
|
#define IRQNUM_DEBUG 12
|
|
#define IRQNUM_PENDSV 14
|
|
#define IRQNUM_SYSTICK 15
|
|
|
|
#define CMD_IS_PRESENT 0x00
|
|
#define CMD_SET_INTERRUPT_ACTIVE 0x01
|
|
#define CMD_SET_INTERRUPT_INACTIVE 0x02
|
|
#define CMD_GET_EXCEPTION_PRIORITY 0x03
|
|
#define CMD_GET_HIGHEST_PRIORITY 0x04
|
|
#define CMD_GET_ACTIVE_EXCEPTION_COUNT 0x05
|
|
#define CMD_IS_EXCEPTION_ACTIVE 0x06
|
|
#define CMD_ESCALATE_TO_HARD_FAULT 0x07
|
|
#define CMD_CHANGE_ACTIVE_EXCEPTION 0x08
|