85ef86b22c
Relicensed version taken from: https://www.andreasheinig.de/project:inject Change-Id: I740fd7b0c802e8fc6c1c54eb49830faf61dc8a25
132 lines
4.0 KiB
C
132 lines
4.0 KiB
C
/*
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* ARM JTAG Fault Injector
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*
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* Author: Andreas Heinig <andreas.heinig@gmx.de>
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*
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* Copyright (C) 2011-2014 Department of Computer Science,
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* Design Automation of Embedded Systems Group,
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* Dortmund University of Technology, all rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "arm-opcode.h"
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int verbose_opcode = 0;
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char opcode_string[128];
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char * opcode_string_tmp;
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int decode_instruction(uint32_t inst, arm_regs_t * regs, arm_instruction_t * op)
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{
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memset(op, 0, sizeof(arm_instruction_t));
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op->inst = inst;
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op->regs = regs;
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opcode_string_tmp = opcode_string;
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/* will the instruction be executed ?*/
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uint32_t condtest = op_cond_test(inst, regs->cpsr);
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if(condtest == 0xFFFFFFFF)
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{
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//TODO: parse extension opcodes
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printf("TODO: parse extension opcodes");
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return 1;
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}
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else if(condtest == 0)
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{
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op->flags = OP_FLAG_CONDITION_FALSE;
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return 2;
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}
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uint32_t type = (inst >> 26) & 3;
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switch(type)
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{
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case 0:
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return decode_data_processing(op);
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case 1:
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return decode_load_store(op);
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case 2:
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return decode_load_store_multiple_and_branch(op);
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case 3:
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return decode_coprocessor(op);
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}
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return 1;
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}
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void dump_instruction(const arm_instruction_t * op)
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{
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printf("R0: %08x R1: %08x R2: %08x R3: %08x IP: %08x SP: %08x\n",
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(unsigned int)op->regs->r[0],
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(unsigned int)op->regs->r[1],
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(unsigned int)op->regs->r[2],
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(unsigned int)op->regs->r[3],
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(unsigned int)op->regs->r[12],
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(unsigned int)op->regs->r[13]
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);
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printf("Instruction: %08x PC: %08x LR: %08x CPSR:%08x SPSR:%08x Mem:%08x(%c%c,%u) Flags:%08x\n\tRegisters: r:0x%04x r_fiq:0x%04x w:0x%04x w_fiq:0x%04x -- ",
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(unsigned int)op->inst,
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(unsigned int)op->regs->r[15],
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(unsigned int)op->regs->r[14],
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(unsigned int)op->regs->cpsr,
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(unsigned int)op->regs->spsr,
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(unsigned int)op->mem_addr,
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op->flags & OP_FLAG_READ ? 'R' : ' ',
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op->flags & OP_FLAG_WRITE ? 'W' : ' ',
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(unsigned int)op->mem_size,
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(unsigned int)op->flags,
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(unsigned int)op->regs_r,
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(unsigned int)op->regs_r_fiq,
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(unsigned int)op->regs_w,
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(unsigned int)op->regs_w_fiq
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);
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int i;
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for(i = 0; i < 16; i++)
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{
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if((op->regs_r & (1 << i)) ||
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(op->regs_r_fiq & (1 << i)) ||
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(op->regs_w & (1 << i)) ||
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(op->regs_w_fiq & (1 << i)))
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{
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printf("R%d(", i);
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if(op->regs_r & (1 << i))
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printf("R");
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if(op->regs_r_fiq & (1 << i))
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printf("r");
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if(op->regs_w & (1 << i))
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printf("W");
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if(op->regs_w_fiq & (1 << i))
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printf("w");
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printf("), ");
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}
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}
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printf("\n");
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}
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