85ef86b22c
Relicensed version taken from: https://www.andreasheinig.de/project:inject Change-Id: I740fd7b0c802e8fc6c1c54eb49830faf61dc8a25
156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/*
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* ARM JTAG Fault Injector
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*
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* Author: Andreas Heinig <andreas.heinig@gmx.de>
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*
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* Copyright (C) 2011-2014 Department of Computer Science,
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* Design Automation of Embedded Systems Group,
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* Dortmund University of Technology, all rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include "arm-opcode.h"
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int decode_load_store_multiple_and_branch(arm_instruction_t * op)
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{
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uint32_t inst = op->inst;
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/*
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* Branch ?
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*/
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if(BIT_IS_SET(25))
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{
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uint32_t target = (inst & 0x00FFFFFF) << 8;
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target = ((int32_t)target) >> 6;
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target += op->regs->r[15] + 8;
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if(BIT_IS_SET(24))
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{
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OP_PRINTF("BL\t#0x%08x\n", (unsigned int)target)
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arm_op_add_reg_r(op, 14);
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arm_op_add_reg_w(op, 15);
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return 0;
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}
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else
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{
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OP_PRINTF("B\t#0x%08x\n", (unsigned int)target)
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arm_op_add_reg_w(op, 15);
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return 0;
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}
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}
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/* LDM/STM */
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uint32_t rn = (inst >> 16) & 0xF;
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op->mem_addr = op->regs->r[rn];
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arm_op_add_reg_r(op, rn);
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if(W_SET)
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arm_op_add_reg_w(op, rn);
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if(_L_SET)
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{
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op->flags = OP_FLAG_READ;
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op->regs_w |= (inst & 0x80FF);
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if(IS_OP_FIQ(op) && !(BIT_IS_SET(22)))
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op->regs_w_fiq |= (inst & 0x7F00);
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else
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op->regs_w |= (inst & 0x7F00);
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OP_PRINTF("LDM")
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}
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else
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{
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op->flags = OP_FLAG_WRITE;
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op->regs_r |= (inst & 0x80FF);
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if(IS_OP_FIQ(op) && !(S_SET))
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op->regs_r_fiq |= (inst & 0x7F00);
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else
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op->regs_r |= (inst & 0x7F00);
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OP_PRINTF("STM")
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}
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/* determine memory range size */
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unsigned int i;
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for(i = 0; i < 16; i++)
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{
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if(inst & (1 << i))
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op->mem_size += 4;
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}
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if(!P_SET)
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{
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/* Word addressed by Rn is _included_ in range of memory */
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if(!U_SET)
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{
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/* Downward addressing */
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op->mem_addr -= op->mem_size;
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OP_PRINTF("DA")
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}
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else
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{
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/* Upward addressing */
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// nothing to adjust in this case
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OP_PRINTF("IA")
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}
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}
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else
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{
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/* Word addressed by Rn is _excluded_ in range of memory */
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if(!U_SET)
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{
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/* Downward addressing */
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op->mem_addr -= op->mem_size;
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op->mem_addr -= 4;
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OP_PRINTF("DB")
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}
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else
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{
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/* Upward addressing */
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op->mem_addr += 4;
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OP_PRINTF("IB")
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}
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}
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OP_PRINTF("\tR%d", (int)rn)
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if(W_SET)
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OP_PRINTF("!")
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OP_PRINTF(", {")
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for(i = 0; i < 16; i++)
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{
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if(inst & (1 << i))
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OP_PRINTF("R%d, ", i)
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}
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OP_PRINTF("}")
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if(S_SET)
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OP_PRINTF("^")
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OP_PRINTF(" [Address: %08x]", (unsigned int)op->mem_addr)
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return 0;
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}
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