2575604b41
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_VARIANT_H
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#define ARM_VARIANT_H
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// this defines the architecture options and variants
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typedef enum armArchitectureE {
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// ARCHITECTURE OPTIONS
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ARM_VM = 0x0010, // enable long multiply instructions
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ARM_VT = 0x0020, // enable thumb instructions
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ARM_VD = 0x0040, // enable basic DSP instructions
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ARM_VD2 = 0x0080, // enable LDRD, MCRR, MRRC, PLD and STRD insns
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ARM_SS = 0x0100, // enable supersections, TEX and S bits
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ARM_BX = 0x0200, // enable BX instruction
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ARM_J = 0x0400, // enable trivial Jazelle extension
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ARM_K = 0x0800, // enable multi-processing instructions
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ARM_VT2 = 0x1000, // enable Thumb-2 instructions
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// ARCHITECTURE VERSIONS
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ARM_V4XM = 4,
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ARM_V4 = 4 | ARM_VM,
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ARM_V4TXM = 4 | ARM_BX | ARM_VT,
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ARM_V4T = 4 | ARM_BX | ARM_VM | ARM_VT,
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ARM_V5XM = 5 | ARM_BX,
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ARM_V5 = 5 | ARM_BX | ARM_VM,
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ARM_V5TXM = 5 | ARM_BX | ARM_VT,
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ARM_V5T = 5 | ARM_BX | ARM_VM | ARM_VT,
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ARM_V5TEXP = 5 | ARM_BX | ARM_VM | ARM_VT | ARM_VD,
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ARM_V5TE = 5 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS,
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ARM_V5TEJ = 5 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS | ARM_J,
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ARM_V6 = 6 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS | ARM_J,
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ARM_V6K = 6 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS | ARM_J | ARM_K,
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ARM_V6T2 = 6 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS | ARM_J | ARM_VT2,
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ARM_V7 = 7 | ARM_BX | ARM_VM | ARM_VT | ARM_VD | ARM_VD2 | ARM_SS | ARM_J | ARM_K | ARM_VT2
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} armArchitecture;
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// this defines thumb versions
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typedef enum armThumbVersionE {
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ARM_THUMB_NONE, // no thumb instructions
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ARM_THUMB_V1, // version 1 thumb instructions
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ARM_THUMB_V2 // version 2 thumb instructions
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} armThumbVersion;
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// this selects armArchitecture bits specifying instruction version
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#define ARM_MASK_VERSION 0xf
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// this is used to restrict availability of features to certain variants
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#define ARM_SUPPORT(_V, _M) (((_V) & (_M)) == (_M))
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// get the main instruction set version
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#define ARM_INSTRUCTION_VERSION(_V) ((_V) & ARM_MASK_VERSION)
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// get the thumb instruction set version
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#define ARM_THUMB_VERSION(_V) ( \
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!ARM_SUPPORT(_V, ARM_VT) ? ARM_THUMB_NONE : \
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(ARM_INSTRUCTION_VERSION(_V)==4) ? ARM_THUMB_V1 : ARM_THUMB_V2 \
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)
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// get architecture index for the passed variant
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#define ARM_VARIANT_ARCH(_V) \
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({ \
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Uns32 _IV = ARM_INSTRUCTION_VERSION(_V); \
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(_IV>=7) ? 0xf : \
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(_IV==6) ? 0x7 : \
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(_IV==5) && ((_V)&ARM_J) ? 0x6 : \
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(_IV==5) && ((_V)&ARM_VD2) ? 0x5 : \
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(_IV==5) && ((_V)&ARM_VT) ? 0x4 : \
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(_IV==5) ? 0x3 : \
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(_IV==4) && ((_V)&ARM_VT) ? 0x2 : \
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(_IV==4) ? 0x1 : 0x0; \
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})
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#endif
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