64034e29b4
This change implements what the source-code comment already promised but didn't keep: As we only record time deltas instead of absolute time values, prevtime must not be overwritten unless the current delta was really added to the trace. This has caused timing information to be stored incorrectly if certain events were skipped (e.g., because they didn't match the memory map configured by the user). Change-Id: Id40271d117dd91b1122136c62329d64174f304b0
136 lines
3.5 KiB
C++
136 lines
3.5 KiB
C++
#include <iostream>
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#include <assert.h>
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#include "sal/SALInst.hpp"
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#include "sal/Register.hpp"
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#include "sal/Memory.hpp"
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#include "sal/Listener.hpp"
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#include "TracingPlugin.hpp"
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using namespace std;
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using namespace fail;
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bool TracingPlugin::run()
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{
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MemoryManager& mm = simulator.getMemoryManager();
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MemAccessListener ev_mem(ANY_ADDR);
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BPSingleListener ev_step(ANY_ADDR);
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BaseListener *ev = 0;
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// ev_step is added in the first loop iteration
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if (m_memonly || !m_iponly) {
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simulator.addListener(&ev_mem);
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}
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if(m_protoStreamFile) {
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ps = new ProtoOStream(m_protoStreamFile);
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}
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UniformRegisterSet *extended_trace_regs =
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simulator.getCPU(0).getRegisterSetOfType(RT_TRACE);
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// the first event gets an absolute time stamp, all others a delta to their
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// predecessor
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simtime_t prevtime = 0, curtime;
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simtime_diff_t deltatime;
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bool first = true;
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while (true) {
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curtime = simulator.getTimerTicks();
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deltatime = curtime - prevtime;
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if (ev == &ev_step || (first && (m_iponly || !m_memonly))) {
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first = false;
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simulator.addListener(&ev_step);
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address_t ip = simulator.getCPU(0).getInstructionPointer();
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if (m_ipMap && !m_ipMap->isMatching(ip)) {
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continue;
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}
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if (m_os)
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*m_os << "[Tracing] IP " << hex << ip << "\n";
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if (m_protoStreamFile) {
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Trace_Event e;
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e.set_ip(ip);
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// only store deltas != 0
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if (deltatime != 0) {
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e.set_time_delta(deltatime);
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// do this only if the last delta was written
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// (no, e.g., memory map mismatch)
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prevtime = curtime;
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}
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ps->writeMessage(&e);
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}
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} else if (ev == &ev_mem) {
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simulator.addListener(&ev_mem);
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address_t ip = ev_mem.getTriggerInstructionPointer();
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address_t addr = ev_mem.getTriggerAddress();
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size_t width = ev_mem.getTriggerWidth();
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if ((m_ipMap && !m_ipMap->isMatching(ip)) ||
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(m_memMap && !m_memMap->isMatching(addr, width))) {
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continue;
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}
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if (m_os)
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*m_os << hex << "[Tracing] MEM "
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<< ((ev_mem.getTriggerAccessType() &
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MemAccessEvent::MEM_READ) ? "R " : "W ")
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<< addr << " width " << width << " IP " << ip << "\n";
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if (m_protoStreamFile) {
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Trace_Event e;
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e.set_ip(ip);
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e.set_memaddr(addr);
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e.set_width(width);
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e.set_accesstype(
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(ev_mem.getTriggerAccessType() & MemAccessEvent::MEM_READ) ?
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e.READ : e.WRITE);
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// only store deltas != 0
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if (deltatime != 0) {
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e.set_time_delta(deltatime);
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// do this only if the last delta was written
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// (no, e.g., memory map mismatch)
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prevtime = curtime;
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}
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/* When we're doing a full trace, we log more data in
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the case of a memory event */
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if (m_full_trace) {
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Trace_Event_Extended &ext = *e.mutable_trace_ext();
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// Read the accessed data
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assert(width <= 8);
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uint64_t data = 0;
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mm.getBytes(addr, width, &data);
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ext.set_data(data);
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for (UniformRegisterSet::iterator it = extended_trace_regs->begin();
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it != extended_trace_regs->end(); ++it) {
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Trace_Event_Extended_Registers *er = ext.add_registers();
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er->set_id((*it)->getId());
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er->set_value(simulator.getCPU(0).getRegisterContent(*it));
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if (er->value() <= mm.getPoolSize() - 4) {
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uint32_t value_deref;
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mm.getBytes(er->value(), 4, &value_deref);
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er->set_value_deref(value_deref);
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}
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}
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}
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ps->writeMessage(&e);
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}
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} else if (!first) {
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if (m_os)
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*m_os << "[Tracing] SOMETHING IS SERIOUSLY WRONG\n";
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}
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ev = simulator.resume();
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}
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return true;
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}
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