4e3c9e3758
The extended trace register list is needed in multiple locations; the CPU class is the logical module to contain this information. Increased number of x86 registers to be traced; we can remove those that prove unusable for fault-space pruning later on. Change-Id: Ic46ecdbc55167a6d92872c190317fc0d1a3ad92d
Some hints on memory-access tracing in Bochs:
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- Instruction fetches: no memory accesses!
- INC ${MEM_ADDR} (increment in memory): a read and a write access
- CALL ${INSTR_ADDR} (call function): a single write access
- PUSH %{REG} (push on stack): dito
- PUSHF (push on stack): dito
- INT ${INTERRUPT#} (interrupt trigger): 3 write accesses