85ef86b22c
Relicensed version taken from: https://www.andreasheinig.de/project:inject Change-Id: I740fd7b0c802e8fc6c1c54eb49830faf61dc8a25
141 lines
4.4 KiB
C
141 lines
4.4 KiB
C
/*
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* ARM JTAG Fault Injector
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*
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* Author: Andreas Heinig <andreas.heinig@gmx.de>
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*
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* Copyright (C) 2011-2014 Department of Computer Science,
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* Design Automation of Embedded Systems Group,
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* Dortmund University of Technology, all rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ARM_OPCODE_H__INCLUDED__
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#define ARM_OPCODE_H__INCLUDED__
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#include <stdint.h>
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typedef struct {
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uint32_t r[16]; // registers of current mode only!
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uint32_t cpsr;
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uint32_t spsr;
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} arm_regs_t;
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extern int verbose_opcode;
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extern char opcode_string[128];
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extern char * opcode_string_tmp;
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#define OP_PRINTF(fmt, arg...) { if(verbose_opcode) printf(fmt, ##arg); }
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//#define OP_PRINTF(fmt, arg...) printf(fmt, ##arg)
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//#define OP_PRINTF(fmt, arg...) opcode_string_tmp += sprintf(opcode_string_tmp, fmt, ##arg)
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#define BIT_IS_SET(bit) (inst & (1 << bit))
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#define BIT_IS_CLEAR(bit) (!(inst & (1 << bit)))
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#define ARM_MODE_MASK 0x1F
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_UND 0x1B
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_USR 0x10
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#define ARM_MODE_SYS 0x1F
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#define IS_OP_FIQ(op) ((((op)->regs->cpsr) & ARM_MODE_MASK) == ARM_MODE_FIQ)
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#define I_BIT (1 << 25)
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#define P_BIT (1 << 24)
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#define U_BIT (1 << 23)
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#define B_BIT (1 << 22)
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#define S_BIT (1 << 22)
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#define ALU_S_BIT (1 << 20)
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#define W_BIT (1 << 21)
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#define L_BIT (1 << 20)
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#define I_SET (inst & I_BIT)
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#define P_SET (inst & P_BIT)
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#define U_SET (inst & U_BIT)
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#define B_SET (inst & B_BIT)
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#define S_SET (inst & S_BIT)
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#define ALU_S_SET (inst & ALU_S_BIT)
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#define W_SET (inst & W_BIT)
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#define _L_SET (inst & L_BIT)
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#define OP_FLAG_WRITE 0x00000001
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#define OP_FLAG_READ 0x00000002
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#define OP_FLAG_CONDITION_FALSE 0x80000000
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typedef struct {
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uint32_t inst;
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arm_regs_t * regs;
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uint32_t flags;
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uint32_t regs_r;
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uint32_t regs_r_fiq;
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uint32_t regs_w;
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uint32_t regs_w_fiq;
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uint32_t mem_addr;
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uint32_t mem_size;
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}arm_instruction_t;
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uint32_t op_cond_test(uint32_t inst, uint32_t cpsr);
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uint32_t decode_addressing_mode1(arm_instruction_t * op);
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void decode_addressing_mode2(arm_instruction_t * op);
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void decode_addressing_mode3(arm_instruction_t * op);
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void decode_addressing_mode5(arm_instruction_t * op);
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int decode_data_processing(arm_instruction_t * op);
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int decode_load_store(arm_instruction_t * op);
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int decode_load_store_multiple_and_branch(arm_instruction_t * op);
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int decode_coprocessor(arm_instruction_t * op);
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int decode_instruction(uint32_t inst, arm_regs_t * regs, arm_instruction_t * op);
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void dump_instruction(const arm_instruction_t * op);
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static inline void arm_op_add_reg_r(arm_instruction_t * op, uint32_t r)
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{
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if(r >= 8 && IS_OP_FIQ(op))
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op->regs_r_fiq |= (1 << r);
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else
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op->regs_r |= (1 << r);
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}
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static inline void arm_op_add_reg_w(arm_instruction_t * op, uint32_t r)
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{
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if(r >= 8 && r != 15 && IS_OP_FIQ(op))
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op->regs_w_fiq |= (1 << r);
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else
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op->regs_w |= (1 << r);
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}
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#endif /* ARM_OPCODE_H__INCLUDED__ */
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