b70b6fb43a
"failstar" sounds like a name for a cruise liner from the 80s. As "*" isn't a desirable part of directory names, just name the whole thing "fail/", the core parts being stored in "fail/core/". Additionally fixing two build system dependency issues: - missing jobserver -> protomessages dependency - broken bochs -> fail dependency (add_custom_target DEPENDS only allows plain file dependencies ... cmake for the win) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@956 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_UTILS_H
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#define ARM_UTILS_H
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// model header files
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#include "armTypeRefs.h"
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//
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// Set the initial endianness for the model
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//
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void armSetInitialEndian(armP arm, Bool isBigEndian);
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//
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// Return the name of a GPR
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//
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const char *armGetGPRName(armP arm, Uns32 index);
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//
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// Return the name of a CPR
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//
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const char *armGetCPRName(armP arm, Uns32 index);
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//
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// Update processor block mask
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//
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void armSetBlockMask(armP arm);
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//
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// Switch banked registers on switch to the passed mode
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//
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void armSwitchRegs(armP arm, Bool oldUseSPProcess, Bool newUseSPProcess);
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//
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// Write CONTROL.SP_PROCESS field
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//
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void armWriteSPProcess(armP arm, Bool newSPProcess);
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//
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// Read CPSR register
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//
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Uns32 armReadCPSR(armP arm);
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//
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// Write CPSR register
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//
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void armWriteCPSR(armP arm, Uns32 value, Uns32 mask);
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//
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// Write PRIMASK register
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//
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void armWritePRIMASK(armP arm, Uns32 value);
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//
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// Write BASEPRI register
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//
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void armWriteBASEPRI(armP arm, Uns32 value);
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//
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// Write BASEPRI register (using BASEPRI_MAX semantics)
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//
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void armWriteBASEPRI_MAX(armP arm, Uns32 value);
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//
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// Write FAULTMASK register
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//
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void armWriteFAULTMASK(armP arm, Uns32 value);
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//
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// read CONTROL register
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//
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Uns32 armReadCONTROL(armP arm);
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//
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// Write CONTROL register
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//
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void armWriteCONTROL(armP arm, Uns32 value);
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//
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// update the CONTROL.FPCA bit to the value. If it changes then set the block mask
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//
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void armUpdateFPCA(armP arm, Bool value);
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//
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// update the FPCCR.LSPACT bit to the value. If it changes then set the block mask
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//
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void armUpdateLSPACT(armP arm, Bool value);
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//
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// Write SP register
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//
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void armWriteSP(armP arm, Uns32 value);
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//
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// Switch processor mode if required
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//
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void armSwitchMode(armP arm);
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//
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// Abort any active exclusive access
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//
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void armAbortExclusiveAccess(armP arm);
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#endif
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