2575604b41
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
360 lines
14 KiB
C
360 lines
14 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_STRUCTURE_H
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#define ARM_STRUCTURE_H
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// VMI header files
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#include "vmi/vmiPorts.h"
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#include "vmi/vmiTypes.h"
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// model header files
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#include "armConfig.h"
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#include "armExceptionTypes.h"
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#include "armSysRegisters.h"
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#include "armMode.h"
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#include "armTypeRefs.h"
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#include "armVariant.h"
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// processor debug flags
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#define ARM_DISASSEMBLE_MASK 0x00000001
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#define ARM_THUMB_MASK 0x00000002
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#define ARM_DEBUG_MMU_MASK 0x00000004
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#define ARM_DEBUG_EXCEPT_MASK 0x00000008
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#define ARM_DUMP_SDFP_REG_MASK 0x00000010
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#define ARM_DISASSEMBLE(_P) ((_P)->flags & ARM_DISASSEMBLE_MASK)
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#define ARM_THUMB(_P) ((_P)->flags & ARM_THUMB_MASK)
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#define ARM_DEBUG_MMU(_P) ((_P)->flags & ARM_DEBUG_MMU_MASK)
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#define ARM_DEBUG_EXCEPT(_P) ((_P)->flags & ARM_DEBUG_EXCEPT_MASK)
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#define ARM_DUMP_SDFP_REG(_P) ((_P)->flags & ARM_DUMP_SDFP_REG_MASK)
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#define ARM_GPR_BITS 32
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#define ARM_GPR_BYTES (ARM_GPR_BITS/8)
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#define ARM_GPR_NUM 16
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#define ARM_TEMP_NUM 12
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#define ARM_VFP_REG_BITS 64
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#define ARM_VFP_REG_BYTES 8
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#define ARM_VFP16_REG_NUM 16
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#define ARM_VFP32_REG_NUM 32
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#define ARM_EXCEPT_NUM 512
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#define ARM_EXCEPT_MASK_NUM ((ARM_EXCEPT_NUM+31)/32)
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#define ARM_INTERRUPT_NUM 496
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#define ARM_NO_TAG -1
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// simulator compatibility modes
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typedef enum armCompatModeE {
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COMPAT_ISA, // conform to the documented ISA
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COMPAT_GDB, // conform to gdb simulator
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COMPAT_CODE_SOURCERY // conform to ARM CodeSourcery toolchain output (ignore BKPT)
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} armCompatMode;
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// arithmetic flags
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typedef struct armArithFlagsS {
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Uns8 ZF; // zero flag
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Uns8 NF; // sign flag
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Uns8 CF; // carry flag
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Uns8 VF; // overflow flag
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} armArithFlags;
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// other flags
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typedef struct armOtherFlagsS {
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Uns8 HI; // hi flag (created on demand)
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Uns8 LT; // lt flag (created on demand)
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Uns8 LE; // le flag (created on demand)
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Uns8 QF; // saturation flag
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} armOtherFlags;
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// ARM PSR (combines APSR, IPSR and EPSR)
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typedef union armPSRU {
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struct {
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Uns32 exceptNum : 9; // exception number
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Uns32 align4 : 1; // 4 byte alignment (in stack)
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Uns32 IT72 : 6; // if-then state, bits 7:2
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Uns32 GE : 4; // GE bits (unused when no DSP)
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Uns32 _u1 : 4; // unused bits
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Uns32 T : 1; // Thumb mode bit
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Uns32 IT10 : 2; // if-then state, bits 1:0
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Uns32 Q : 1; // DSP overflow/saturate flag
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Uns32 V : 1; // overflow flag
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Uns32 C : 1; // carry flag
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Uns32 Z : 1; // zero flag
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Uns32 N : 1; // sign flag
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} fields;
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Uns32 reg;
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} armPSR;
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// PSR Access Macros
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#define PSR_FIELD(_A, _F) ((_A)->sregs.PSR.fields._F)
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#define IN_USER_MODE(_A) (!PSR_FIELD(_A, exceptNum) && CONTROL_FIELD(_A, threadUnpriv))
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#define IN_THUMB_MODE(_A) PSR_FIELD(_A, T)
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#define IN_HANDLER_MODE(_A) (PSR_FIELD(_A, exceptNum) && True)
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#define IN_BASE_MODE(_A) IN_USER_MODE(_A)
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#define IN_PRIV_MPU_MODE(_A) (!IN_USER_MODE(_A) && MPU_ENABLED(_A))
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// Masks for fields in PSR
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#define PSR_FLAGS 0xf8000000
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#define PSR_NZCV 0xf0000000
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#define PSR_EXCEPT_NUM 0x000001ff
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#define PSR_THUMB 0x01000000
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#define PSR_IT10 0x06000000
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#define PSR_IT72 0x0000fc00
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#define PSR_GE 0x000f0000
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#define PSR_GE3 0x00080000
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#define PSR_GE2 0x00040000
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#define PSR_GE1 0x00020000
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#define PSR_GE0 0x00010000
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#define PSR_GE32 (PSR_GE3|PSR_GE2)
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#define PSR_GE10 (PSR_GE1|PSR_GE0)
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#define PSR_GE30 (PSR_GE32|PSR_GE10)
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#define PSR_IT (PSR_IT72 | PSR_IT10)
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#define PSR_ALL (PSR_FLAGS | PSR_IT | PSR_THUMB | PSR_GE | PSR_EXCEPT_NUM)
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#define PSR_NOT_FLAGS (PSR_ALL & ~(PSR_FLAGS | PSR_GE))
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// ARM CONTROL
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typedef union armCONTROLU {
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struct {
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Uns32 threadUnpriv : 1; // is thread mode unprivileged?
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Uns32 useSP_Process : 1; // use SP_process stack
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Uns32 FPCA : 1; // Is FP active in current context?
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} fields;
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Uns32 reg;
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} armCONTROL;
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// CONTROL Access Macros
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#define CONTROL_FIELD(_A, _F) ((_A)->sregs.CONTROL.fields._F)
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#define USE_SP_PROCESS(_A) CONTROL_FIELD(_A, useSP_Process)
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// Masks for fields in CONTROL
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#define CONTROL_FPCA 0x00000004
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// ARM FPSCR
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typedef union armFPSCRU {
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struct {
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Uns32 IOC : 1;
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Uns32 DZC : 1;
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Uns32 OFC : 1;
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Uns32 UFC : 1;
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Uns32 IXC : 1;
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Uns32 _u1 : 2;
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Uns32 IDC : 1;
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Uns32 _u2 : 14;
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Uns32 RMode : 2;
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Uns32 FZ : 1;
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Uns32 DN : 1;
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Uns32 AHP : 1;
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Uns32 _u3 : 1;
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Uns32 V : 1;
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Uns32 C : 1;
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Uns32 Z : 1;
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Uns32 N : 1;
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} fields;
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Uns32 reg;
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} armFPSCR;
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// FPSCR Access Macros
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#define FPSCR_MASK 0xf7c0009f
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#define FPSCR_REG(_A) ((_A)->sregs.FPSCR.reg)
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#define FPSCR_FIELD(_A, _F) ((_A)->sregs.FPSCR.fields._F)
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// Write Masks for fields in other control registers (with no structs)
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#define PRIMASK_MASK 0x00000001
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#define FAULTMASK_MASK 0x00000001
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#define BASEPRI_MASK 0x000000ff
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// Special register definitions
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typedef struct armSpecialRegsS {
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armPSR PSR;
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armCONTROL CONTROL;
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Uns32 PRIMASK;
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Uns32 FAULTMASK;
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Uns32 BASEPRI;
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armFPSCR FPSCR;
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} armSpecialRegs;
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// Banked registers
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typedef struct armBankRegsS {
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// process stack pointer
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Uns32 R13_process;
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} armBankRegs;
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typedef struct armDomainSetS {
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memDomainP external; // external memory domain
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memDomainP vmPriv; // virtual code domain, privileged mode
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memDomainP vmUser; // virtual code domain, user mode
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memDomainP system; // system domain
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} armDomainSet, *armDomainSetP;
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typedef enum armPIDSetE {
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APS_PHYS, // physical domains (privileged or user mode)
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APS_VM_P, // MMU/MPU-managed privileged mode domains
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APS_VM_U, // MMU/MPU-managed user mode domains
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APS_LAST // KEEP LAST: for sizing
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} armPIDSet;
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// decoder callback function to decode instruction at the passed address
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#define ARM_DECODER_FN(_NAME) void _NAME( \
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armP arm, \
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Uns32 thisPC, \
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armInstructionInfoP info \
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)
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typedef ARM_DECODER_FN((*armDecoderFn));
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// Callback function to return size of instruction at the passed for the specified mode
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#define ARM_ISIZE_FN(_NAME) Uns32 _NAME( \
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armP arm, \
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Uns32 thisPC, \
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Bool isThumb \
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)
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typedef ARM_ISIZE_FN((*armIsizeFn));
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// opaque type for MPU protection region
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typedef struct protRegionS *protRegionP;
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// VFP register bank
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typedef union armVFPRS {
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Uns8 b[ARM_VFP16_REG_NUM*8]; // when viewed as bytes
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Uns16 h[ARM_VFP16_REG_NUM*4]; // When viewed as 16 bit halfwords
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Uns32 w[ARM_VFP16_REG_NUM*2]; // when viewed as 32-bit words
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Uns64 d[ARM_VFP16_REG_NUM]; // when viewed as 64-bit double words
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} armVFPR;
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#define FP_REG(_A, _I) ((_A)->vregs.w[(_I)])
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// floating point control word type
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typedef union armFPCWU {
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Uns32 u32; // when viewed as composed value
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vmiFPControlWord cw; // when viewed as fields
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} armFPCW;
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// processor structure
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typedef struct armS {
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// TRUE PROCESSOR REGISTERS
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armArithFlags aflags; // arithmetic flags
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armOtherFlags oflags; // other flags
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Uns32 regs[ARM_GPR_NUM]; // current mode GPRs
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armSpecialRegs sregs; // special purpose registers
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// SIMULATOR SUPPORT
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Uns32 temps[ARM_TEMP_NUM]; // temporary registers
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Uns8 itStateRT; // if-then state (run time)
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Uns8 itStateMT; // if-then state (morph time)
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Uns8 divideTarget; // target of divide instruction
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Uns8 disableReason; // reason why processor disabled
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Bool eventRegister; // event register
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Bool pendingInterrupt; // is interrupt pending?
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armMode mode :8; // current processor mode
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Bool validHI :1; // is hi flag valid?
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Bool validLT :1; // is lt flag valid?
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Bool validLE :1; // is le flag valid?
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Bool checkEndian :1; // check endian using blockMask?
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Bool checkL4 :1; // check interwork using blockMask?
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Bool checkUnaligned :1; // check alignment mode using blockMask?
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Bool disableTimerRVR0 :1; // disable timer (SYST_RVR==0)?
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Bool sleepOnExit :1; // sleeping at exception exit?
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Bool denormalInput :1; // input denormal sticky flag
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memEndian instructionEndian:1; // instruction endianness
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armExceptCxt exceptionContext :3; // exception context
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Uns32 exclusiveTag; // tag for active exclusive access
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Uns32 exclusiveTagMask; // mask to select exclusive tag bits
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Uns32 priorityMask; // priority mask
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Uns32 exceptNum; // total number of exceptions
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Uns32 exceptMaskNum; // number of words in exception masks
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Uns32 timerModulus; // modulus value for counter
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Uns64 timerBase; // nominal counter base value
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// SYSTEM AND BANKED REGISTERS (INFREQUENTLY USED AT RUN TIME)
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armBankRegs bank; // banked registers
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armSCSRegs scs; // SCS registers
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// VFP REGISTERS
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armFPCW currentCW; // current control word
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armArithFlags sdfpAFlags; // FPU comparison flags
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Uns8 sdfpFlags; // FPU operation flags
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Uns8 sdfpSticky; // FPU sticky flags
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armVFPR vregs; // VFP data registers
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// VARIANT CONFIGURATION
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Uns32 flags; // configuration flags
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armConfig configInfo; // configuration register defaults
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armCompatMode compatMode :2; // compatibility mode
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Bool simEx :1; // simulate exceptions?
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Bool verbose :1; // verbose messages enabled?
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Bool showHiddenRegs :1; // show hidden registers in reg dump
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Bool UAL :1; // disassemble using UAL syntax
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Bool disableBitBand :1; // bit banding disabled
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// MEMORY SUBSYSTEM SUPPORT
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Bool restoreDomain :1; // whether to resore domain (LDRT, STRT)
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protRegionP impu; // instruction/unified MPU
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protRegionP dmpu; // data MPU (if not unified)
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armDomainSet ids; // instruction domain set
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armDomainSet dds; // data domain set
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// NET HANDLES (used for NVIC)
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Uns32 sysResetReq; // system reset requested
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Uns32 intISS; // interrupt service started
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Uns32 eventOut; // event output signal
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Uns32 lockup; // lockup output signal
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// EXCEPTION SUPPORT
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Int32 unboostedPriority; // unboosted execution priority
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Int32 executionPriority; // current execution priority
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armExceptNum enabledException; // current enabled exception
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armExceptNum pendingException; // current pending exception
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armExceptNum derivedException; // pushStack/popStack exception
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Uns32 nestedActivation; // used for handler->thread check
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Uns32 xPend[ARM_EXCEPT_MASK_NUM]; // pending exceptions
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Uns32 xActive[ARM_EXCEPT_MASK_NUM];// active exceptions
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Uns32 xEnable[ARM_EXCEPT_MASK_NUM];// exception enables
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Uns8 xPriority[ARM_EXCEPT_NUM]; // exception priorities
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vmiNetPortP netPorts; // net ports on this variant
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memDomainP FPCARdomain; // memory domain associated with the FPCAR
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// INTERCEPT LIBRARY SUPPORT
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armDecoderFn decoderCB; // generic instruction decoder
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armIsizeFn isizeCB; // instruction size callback
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} arm;
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#endif
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