2575604b41
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
123 lines
5.2 KiB
C
123 lines
5.2 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_REGISTERS_H
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#define ARM_REGISTERS_H
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// VMI header files
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#include "vmi/vmiTypes.h"
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// model header files
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#include "armTypeRefs.h"
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////////////////////////////////////////////////////////////////////////////////
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// REGISTER ACCESS MACROS
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////////////////////////////////////////////////////////////////////////////////
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// aliases for specific GPRs
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#define ARM_REG_SP 13
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#define ARM_REG_LR 14
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#define ARM_REG_PC 15
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// morph-time macros to calculate offsets to registers in an arm structure
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#define ARM_CPU_OFFSET(_F) VMI_CPU_OFFSET(armP, _F)
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#define ARM_CPU_REG(_F) VMI_CPU_REG(armP, _F)
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#define ARM_CPU_REG_CONST(_F) VMI_CPU_REG_CONST(armP, _F)
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#define ARM_CPU_TEMP(_F) VMI_CPU_TEMP(armP, _F)
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// morph-time macros to calculate constant offsets to flags in an arm structure
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#define ARM_ZF_CONST ARM_CPU_REG_CONST(aflags.ZF)
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#define ARM_NF_CONST ARM_CPU_REG_CONST(aflags.NF)
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#define ARM_CF_CONST ARM_CPU_REG_CONST(aflags.CF)
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#define ARM_VF_CONST ARM_CPU_REG_CONST(aflags.VF)
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#define ARM_HI_CONST ARM_CPU_REG_CONST(oflags.HI)
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#define ARM_LT_CONST ARM_CPU_REG_CONST(oflags.LT)
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#define ARM_LE_CONST ARM_CPU_REG_CONST(oflags.LE)
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// morph-time macros to calculate variable offsets to flags in an arm structure
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#define ARM_AFLAGS ARM_CPU_REG(aflags)
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#define ARM_ZF ARM_CPU_REG(aflags.ZF)
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#define ARM_NF ARM_CPU_REG(aflags.NF)
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#define ARM_CF ARM_CPU_REG(aflags.CF)
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#define ARM_VF ARM_CPU_REG(aflags.VF)
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#define ARM_QF ARM_CPU_REG(oflags.QF)
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// morph-time macros to calculate offsets to fields in an arm structure
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#define ARM_REG(_R) ARM_CPU_REG(regs[_R])
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#define ARM_TREG(_R) ARM_CPU_TEMP(regs[_R])
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#define ARM_TEMP(_R) ARM_CPU_TEMP(temps[_R])
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#define ARM_SP ARM_REG(ARM_REG_SP)
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#define ARM_LR ARM_REG(ARM_REG_LR)
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#define ARM_PC ARM_TREG(ARM_REG_PC)
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// morph-time macros to calculate offsets to control registers
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#define ARM_PSR ARM_CPU_REG(sregs.PSR)
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#define ARM_CONTROL ARM_CPU_REG(sregs.CONTROL)
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#define ARM_PRIMASK ARM_CPU_REG(sregs.PRIMASK)
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#define ARM_FAULTMASK ARM_CPU_REG(sregs.FAULTMASK)
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#define ARM_BASEPRI ARM_CPU_REG(sregs.BASEPRI)
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#define ARM_FPSCR ARM_CPU_REG(sregs.FPSCR)
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// morph-time macros to calculate offsets to banked registers in an arm structure
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#define ARM_BANK_REG(_N, _SET) ARM_CPU_REG(bank.R##_N##_##_SET)
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#define ARM_BANK_SP ARM_BANK_REG(13, process)
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// morph-time macro to calculate offset to EA tag in an arm structure
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#define ARM_EA_TAG ARM_CPU_REG(exclusiveTag)
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// morph-time macro to calculate offset to ITSTATE in an arm structure
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#define ARM_IT_STATE ARM_CPU_REG(itStateRT)
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// morph-time macro to calculate offset to divide target index in an arm structure
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#define ARM_DIVIDE_TARGET ARM_CPU_REG(divideTarget)
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// morph-time macro to calculate offset to disable reason, event register and
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// pending interrupt state in an arm structure
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#define ARM_DISABLE_REASON ARM_CPU_REG(disableReason)
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#define ARM_EVENT ARM_CPU_REG(eventRegister)
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#define ARM_PENDING ARM_CPU_REG(pendingInterrupt)
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// morph-time macros to calculate offsets to floating point registers in an arm
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// structure
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#define ARM_FP_FLAGS ARM_CPU_REG(sdfpFlags)
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#define ARM_FP_STICKY ARM_CPU_REG(sdfpSticky)
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#define ARM_BREG(_R) ARM_CPU_REG(vregs.b[_R])
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#define ARM_HREG(_R) ARM_CPU_REG(vregs.h[_R])
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#define ARM_WREG(_R) ARM_CPU_REG(vregs.w[_R])
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#define ARM_DREG(_R) ARM_CPU_REG(vregs.d[_R])
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#endif
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