2575604b41
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
214 lines
11 KiB
C
214 lines
11 KiB
C
/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_DISASSEMBLE_FORMATS_H
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#define ARM_DISASSEMBLE_FORMATS_H
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//
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// These are placeholders in disassembly decoder
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//
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#define EMIT_R1 '\001'
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#define EMIT_R2 '\002'
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#define EMIT_R3 '\003'
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#define EMIT_R4 '\004'
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#define EMIT_CU '\005'
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#define EMIT_CS '\006'
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#define EMIT_CX '\007'
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#define EMIT_T '\010'
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#define EMIT_SHIFT '\011'
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#define EMIT_SHIFT_C '\012'
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#define EMIT_CPNUM '\013'
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#define EMIT_COP1 '\014'
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#define EMIT_COP2 '\015'
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#define EMIT_CR1 '\016'
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#define EMIT_CR2 '\017'
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#define EMIT_CR3 '\020'
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#define EMIT_OPT '\021'
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#define EMIT_WB '\022'
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#define EMIT_RLIST '\023'
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#define EMIT_U '\024'
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#define EMIT_SR '\025'
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#define EMIT_FLAGS '\026'
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#define EMIT_OPT_MODE '\027'
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#define EMIT_LIM '\031'
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#define EMIT_WIDTH '\032'
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#define EMIT_ITC '\033'
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#define EMIT_SZSHIFT '\034'
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#define EMIT_R1F '\035'
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#define EMIT_FPSCR '\036'
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#define EMIT_S1 '\302'
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#define EMIT_S2 '\303'
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#define EMIT_S3 '\304'
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#define EMIT_D1 '\305'
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#define EMIT_D2 '\306'
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#define EMIT_D3 '\307'
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#define EMIT_Z1 '\313'
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#define EMIT_Z2 '\314'
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#define EMIT_SS1 '\316'
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#define EMIT_SS3 '\317'
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#define EMIT_C0F '\324'
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#define EMIT_SDFP_MI '\325'
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#define EMIT_SIMD_RL '\326'
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#define EMIT_VFP_RL '\327'
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//
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// These are placeholders in disassembly format strings
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//
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#define EMIT_R1_S "\001"
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#define EMIT_R2_S "\002"
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#define EMIT_R3_S "\003"
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#define EMIT_R4_S "\004"
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#define EMIT_CU_S "\005"
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#define EMIT_CS_S "\006"
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#define EMIT_CX_S "\007"
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#define EMIT_T_S "\010"
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#define EMIT_SHIFT_S "\011"
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#define EMIT_SHIFT_C_S "\012"
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#define EMIT_CPNUM_S "\013"
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#define EMIT_COP1_S "\014"
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#define EMIT_COP2_S "\015"
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#define EMIT_CR1_S "\016"
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#define EMIT_CR2_S "\017"
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#define EMIT_CR3_S "\020"
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#define EMIT_OPT_S "\021"
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#define EMIT_WB_S "\022"
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#define EMIT_RLIST_S "\023"
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#define EMIT_U_S "\024"
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#define EMIT_SR_S "\025"
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#define EMIT_FLAGS_S "\026"
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#define EMIT_OPT_MODE_S "\027"
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#define EMIT_LIM_S "\031"
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#define EMIT_WIDTH_S "\032"
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#define EMIT_ITC_S "\033"
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#define EMIT_SZSHIFT_S "\034"
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#define EMIT_R1F_S "\035"
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#define EMIT_FPSCR_S "\036"
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#define EMIT_S1_S "\302"
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#define EMIT_S2_S "\303"
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#define EMIT_S3_S "\304"
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#define EMIT_D1_S "\305"
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#define EMIT_D2_S "\306"
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#define EMIT_D3_S "\307"
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#define EMIT_Z1_S "\313"
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#define EMIT_Z2_S "\314"
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#define EMIT_SS1_S "\316"
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#define EMIT_SS3_S "\317"
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#define EMIT_C0F_S "\324"
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#define EMIT_SDFP_MI_S "\325"
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#define EMIT_SIMD_RL_S "\326"
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#define EMIT_VFP_RL_S "\327"
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//
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// These are disassembly format strings
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//
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#define FMT_NONE ""
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#define FMT_R1 EMIT_R1_S
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#define FMT_R1_R2 EMIT_R1_S "," EMIT_R2_S
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#define FMT_R1_R2_R3 EMIT_R1_S "," EMIT_R2_S "," EMIT_R3_S
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#define FMT_R1_R2_R3_R4 EMIT_R1_S "," EMIT_R2_S "," EMIT_R3_S "," EMIT_R4_S
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#define FMT_XIMM EMIT_CX_S
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#define FMT_SIMM EMIT_CS_S
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#define FMT_UIMM EMIT_CU_S
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#define FMT_R1_SIMM EMIT_R1_S "," EMIT_CS_S
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#define FMT_R1_UIMM EMIT_R1_S "," EMIT_CU_S
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#define FMT_R1_R2_SIMM EMIT_R1_S "," EMIT_R2_S "," EMIT_CS_S
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#define FMT_R1_R2_UIMM EMIT_R1_S "," EMIT_R2_S "," EMIT_CU_S
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#define FMT_R1_R2_SHIFT_SIMM EMIT_R1_S "," EMIT_R2_S "," EMIT_SHIFT_C_S
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#define FMT_R1_R2_SHIFT_R3 EMIT_R1_S "," EMIT_R2_S "," EMIT_SHIFT_S " " EMIT_R3_S
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#define FMT_R1_R2_SHIFT EMIT_R1_S "," EMIT_R2_S "," EMIT_SHIFT_S
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#define FMT_R1_R2_R3_SHIFT_SIMM EMIT_R1_S "," EMIT_R2_S "," EMIT_R3_S "," EMIT_SHIFT_C_S
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#define FMT_R1_R2_R3_SHIFT_R4 EMIT_R1_S "," EMIT_R2_S "," EMIT_R3_S "," EMIT_SHIFT_S " " EMIT_R4_S
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#define FMT_R1_R2_R3_SHIFT EMIT_R1_S "," EMIT_R2_S "," EMIT_R3_S "," EMIT_SHIFT_S
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#define FMT_R1_WIDTH_R2 EMIT_R1_S "," EMIT_WIDTH_S "," EMIT_R2_S
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#define FMT_R1_WIDTH_R2_SHIFT_SIMM EMIT_R1_S "," EMIT_WIDTH_S "," EMIT_R2_S "," EMIT_SHIFT_C_S
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#define FMT_R1_ADDR_R2_SIMM EMIT_R1_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]" EMIT_WB_S
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#define FMT_R1_ADDR_R2_R3 EMIT_R1_S ",[" EMIT_R2_S "1]," EMIT_U_S EMIT_R3_S "2]" EMIT_WB_S
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#define FMT_R1_ADDR_R2_R3_SHIFT_SIMM EMIT_R1_S ",[" EMIT_R2_S "1]," EMIT_U_S EMIT_R3_S "," EMIT_SHIFT_C_S "2]" EMIT_WB_S
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#define FMT_R1_ADDR_R2_R3_SHIFT EMIT_R1_S ",[" EMIT_R2_S "1]," EMIT_U_S EMIT_R3_S "," EMIT_SHIFT_S "2]" EMIT_WB_S
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#define FMT_R1_R4_ADDR_R2_SIMM EMIT_R1_S "," EMIT_R4_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]" EMIT_WB_S
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#define FMT_ADDR_R1_SIMM "[" EMIT_R1_S "1],*" EMIT_CS_S "2]" EMIT_WB_S
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#define FMT_ADDR_R1_R2 "[" EMIT_R1_S "1]," EMIT_U_S EMIT_R2_S "2]" EMIT_WB_S
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#define FMT_ADDR_R1_R2_SHIFT_SIMM "[" EMIT_R1_S "1]," EMIT_U_S EMIT_R2_S "," EMIT_SHIFT_C_S "2]" EMIT_WB_S
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#define FMT_ADDR_R1_R2_SHIFT "[" EMIT_R1_S "1]," EMIT_U_S EMIT_R2_S "," EMIT_SHIFT_S "2]" EMIT_WB_S
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#define FMT_R1_R2_ADDR_R3_SIMM EMIT_R1_S "," EMIT_R2_S ",[" EMIT_R3_S "1],*" EMIT_CS_S "2]"
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#define FMT_R1_R2_R4_ADDR_R3_SIMM EMIT_R1_S "," EMIT_R2_S "," EMIT_R4_S ",[" EMIT_R3_S "1],*" EMIT_CS_S "2]"
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#define FMT_R1_R4_ADDR_R2_SIMM EMIT_R1_S "," EMIT_R4_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]" EMIT_WB_S
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#define ADDR_R1_R2_SZSHIFT ",[" EMIT_R1_S "," EMIT_R2_S ",*" EMIT_SZSHIFT_S "]"
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#define FMT_CPNUM_CR1_SIMM EMIT_CPNUM_S "," EMIT_CR1_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]" EMIT_WB_S
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#define FMT_CPNUM_CR1_UNINDEXED EMIT_CPNUM_S "," EMIT_CR1_S ",[" EMIT_R2_S "],{" EMIT_OPT_S "}"
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#define FMT_SR_R1 EMIT_SR_S "," EMIT_R1_S
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#define FMT_R1_SR EMIT_R1_S "," EMIT_SR_S
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#define FMT_R1_WB EMIT_R1_S EMIT_WB_S
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#define FMT_R1_WB_UIMM EMIT_R1_S EMIT_WB_S "," EMIT_CU_S
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#define FMT_T EMIT_T_S
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#define FMT_R1_T EMIT_R1_S "," EMIT_T_S
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#define FMT_CPNUM_COP1_CR1_CR2_CR3_COP2 EMIT_CPNUM_S "," EMIT_COP1_S "," EMIT_CR1_S "," EMIT_CR2_S "," EMIT_CR3_S ",{" EMIT_COP2_S "}"
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#define FMT_CPNUM_COP1_R1_R2_CR3 EMIT_CPNUM_S "," EMIT_COP1_S "," EMIT_R1_S "," EMIT_R2_S "," EMIT_CR3_S
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#define FMT_CPNUM_COP1_R1_CR2_CR3_COP2 EMIT_CPNUM_S "," EMIT_COP1_S "," EMIT_R1_S "," EMIT_CR2_S "," EMIT_CR3_S ",{" EMIT_COP2_S "}"
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#define FMT_CPNUM_COP1_R1F_CR2_CR3_COP2 EMIT_CPNUM_S "," EMIT_COP1_S "," EMIT_R1F_S "," EMIT_CR2_S "," EMIT_CR3_S ",{" EMIT_COP2_S "}"
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#define FMT_RLIST EMIT_RLIST_S
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#define FMT_SIMD_RL EMIT_SIMD_RL_S
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#define FMT_VFP_RL EMIT_VFP_RL_S
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#define FMT_R1_RLIST EMIT_R1_S EMIT_WB_S "," EMIT_RLIST_S
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#define FMT_R1_RLIST_T EMIT_R1_S "!," EMIT_RLIST_S
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#define FMT_R1_RLIST_UM EMIT_R1_S EMIT_WB_S "," EMIT_RLIST_S "^"
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#define FMT_R1_VFP_RL EMIT_R1_S EMIT_WB_S "," EMIT_VFP_RL_S
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#define FMT_R1_SIMD_RL EMIT_R1_S EMIT_WB_S "," EMIT_SIMD_RL_S
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#define FMT_FLAGS_OPT_MODE EMIT_FLAGS_S ",*" EMIT_OPT_MODE_S
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#define FMT_LIM EMIT_LIM_S
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#define FMT_R1_R2_LSB_WIDTH EMIT_R1_S "," EMIT_R2_S "," EMIT_CU_S "," EMIT_WIDTH_S
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#define FMT_R1_LSB_WIDTH EMIT_R1_S "," EMIT_CU_S "," EMIT_WIDTH_S
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#define FMT_ITC EMIT_ITC_S
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#define FMT_R1_FPSCR EMIT_R1F_S "," EMIT_FPSCR_S
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#define FMT_FPSCR_R1 EMIT_FPSCR_S "," EMIT_R1_S
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#define FMT_R1_S2 EMIT_R1_S "," EMIT_S2_S
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#define FMT_R1_Z2 EMIT_R1_S "," EMIT_Z2_S
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#define FMT_S1_F0 EMIT_S1_S "," EMIT_C0F_S
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#define FMT_S1_S2 EMIT_S1_S "," EMIT_S2_S
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#define FMT_S1_R2 EMIT_S1_S "," EMIT_R2_S
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#define FMT_S1_S2_S3 EMIT_S1_S "," EMIT_S2_S "," EMIT_S3_S
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#define FMT_S1_S2_UIMM EMIT_S1_S "," EMIT_S2_S "," EMIT_CU_S
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#define FMT_S1_SDFP_MI EMIT_S1_S "," EMIT_SDFP_MI_S
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#define FMT_S1_ADDR_R2_SIMM EMIT_S1_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]"
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#define FMT_S1_SDFP_MI EMIT_S1_S "," EMIT_SDFP_MI_S
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#define FMT_Z1_R2 EMIT_Z1_S "," EMIT_R2_S
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#define FMT_R1_R2_D3 EMIT_R1_S "," EMIT_R2_S "," EMIT_D3_S
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#define FMT_D1_R2_R3 EMIT_D1_S "," EMIT_R2_S "," EMIT_R3_S
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#define FMT_D1_ADDR_R2_SIMM EMIT_D1_S ",[" EMIT_R2_S "1],*" EMIT_CS_S "2]"
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#define FMT_R1_R2_SS3 EMIT_R1_S "," EMIT_R2_S "," EMIT_SS3_S
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#define FMT_SS1_R2_R3 EMIT_SS1_S "," EMIT_R2_S "," EMIT_R3_S
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#endif
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