08febe5819
Encapsulated gem5-specific code into wrapper functions to separate the build process (Fail: CMake, gem5: scons). Added some gem5-related FIXMEs. Another CMake related FIXME added. +some cosmetics. Change-Id: Id84b480127b1f13aed6a0ee97f3583f410d531c5
102 lines
2.8 KiB
C++
102 lines
2.8 KiB
C++
#include "../SALInst.hpp"
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#include "Gem5Wrapper.hpp"
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#include "Gem5Breakpoint.hpp"
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#include "sim/system.hh"
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#include "mem/packet.hh"
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#include "mem/physical.hh"
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namespace fail {
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// Register-/Memory-related:
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regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx)
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{
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switch (type) {
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case RT_GP:
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if (idx == 15) {
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return sys->getThreadContext(id)->pcState().pc();
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}
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return sys->getThreadContext(id)->readIntReg(idx);
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case RT_FP: return sys->getThreadContext(id)->readFloatReg(idx); // FIXME: correct?! (FP <-> Float?!)
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case RT_ST: return sys->getThreadContext(id)->readMiscReg(idx);
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case RT_IP: return sys->getThreadContext(id)->pcState().pc();
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}
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// This shouldn't be reached if a valid register is passed
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assert(false && "FATAL ERROR: invalid register type (should never be reached)!");
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return 0;
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}
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void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx,
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regdata_t value)
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{
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switch (type) {
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case RT_GP: sys->getThreadContext(id)->setIntReg(idx, value); break;
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case RT_FP: sys->getThreadContext(id)->setFloatReg(idx, value); break; // FIXME: correct?! (FP <-> Float?!)
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case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); break;
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case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); break;
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}
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// This shouldn't be reached if a valid register is passed
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assert(false && "FATAL ERROR: invalid register type (should never be reached)!");
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}
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void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest)
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{
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Request req(addr, cnt, Request::PHYSICAL, 0);
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Packet pkt(&req, MemCmd::ReadReq);
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pkt.dataStatic(dest);
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sys->getPhysMem().functionalAccess(&pkt);
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}
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void WriteMemory(System* sys, guest_address_t addr, size_t cnt, void const *src)
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{
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Request req(addr, cnt, Request::PHYSICAL, 0);
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Packet pkt(&req, MemCmd::WriteReq);
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pkt.dataStatic(src);
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sys->getPhysMem().functionalAccess(&pkt);
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}
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size_t GetPoolSize(System* sys) { return sys->getPhysMem().totalSize(); }
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// Breakpoint-related:
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void Gem5Breakpoint::process(ThreadContext *tc)
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{
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fail::simulator.onBreakpoint(&fail::simulator.getCPU(tc->cpuId()), this->evpc, fail::ANY_ADDR);
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}
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Gem5Breakpoint* OnBreakpointAddition(address_t watchInstrPtr)
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{
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System* sys = *System::systemList.begin();
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// FIXME: begin() vs. front() (see Gem5Controller::startup())
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// FIXME: Provide "sys" using the simulator-inst?
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return new Gem5Breakpoint(&sys->pcEventQueue, watchInstrPtr);
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}
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void OnBreakpointDeletion(Gem5Breakpoint* bp)
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{
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if (bp) {
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delete bp; // TODO: required?
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}
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}
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// Controller-related:
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unsigned int GetCPUId(System* sys, int context)
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{
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return sys->getThreadContext(context)->cpuId();
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}
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System* GetSystemObject()
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{
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return System::systemList.front();
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}
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int GetNumberOfContexts(System* sys)
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{
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return sys->numContexts();
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}
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} // end-of-namespace: fail
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