08febe5819
Encapsulated gem5-specific code into wrapper functions to separate the build process (Fail: CMake, gem5: scons). Added some gem5-related FIXMEs. Another CMake related FIXME added. +some cosmetics. Change-Id: Id84b480127b1f13aed6a0ee97f3583f410d531c5
74 lines
2.5 KiB
C++
74 lines
2.5 KiB
C++
#ifndef __GEM5_ARM_CPU_HPP__
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#define __GEM5_ARM_CPU_HPP__
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#include "../arm/ArmArchitecture.hpp"
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#include "../arm/ArmCPUState.hpp"
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// gem5 forward declarations:
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class System;
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namespace fail {
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/**
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* \class Gem5ArmCPU
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*
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* \c Gem5ArmCPU is the concrete CPU implementation for the gem5 ARM simulator. It
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* implements the CPU interfaces \c ArmArchitecture and \c ArmCPUState.
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* \c ArmArchitecture refers to architectural information (e.g. register \a count)
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* while \c ArmCPUState encapsulates the CPU state (e.g. register \a content).
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*/
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class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState {
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private:
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unsigned int m_Id; //!< the unique ID of this CPU
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System* m_System; //!< the gem5 system object
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public:
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/**
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* Creates a new gem5 CPU for ARM based targets.
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* @param id the unique ID of the CPU to be created (the first CPU0 has ID 0)
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* @param system the gem5 system object
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*/
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Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) { }
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/**
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* Retrieves the register content from the current gem5 CPU.
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* @param reg the destination register whose content should be retrieved
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* @return the content of register \c reg
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*/
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regdata_t getRegisterContent(Register* reg) const;
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/**
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* Sets the register content for the \a current gem5 CPU.
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* @param reg the (initialized) register object whose content should be set
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* @param value the new content of the register \c reg
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*/
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void setRegisterContent(Register* reg, regdata_t value);
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/**
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* Retrieves the current instruction pointer (IP aka program counter, PC for short)
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* for the current CPU \c this.
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* @return the current instruction ptr address
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*/
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address_t getInstructionPointer() const { return getRegisterContent(getRegister(RI_IP)); }
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/**
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* Retrieves the current stack pointer for the current CPU \c this.
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* @return the current stack ptr address
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*/
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address_t getStackPointer() const { return getRegisterContent(getRegister(RI_SP)); }
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/**
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* Retrieves the link register (return address when a function returns) for
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* the current CPU \c this. See
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/ch02s08s01.html
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* for further information.
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* @return the current link register address
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*/
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address_t getLinkRegister() const { return getRegisterContent(getRegister(RI_LR)); }
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/**
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* Returns the ID of the current CPU.
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* @return the unique ID of \c this CPU object
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*/
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unsigned int getId() const { return m_Id; }
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};
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typedef Gem5ArmCPU ConcreteCPU; //!< the concrete CPU type for ARM + gem5
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} // end-of-namespace: fail
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#endif // __GEM5_ARM_CPU_HPP__
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