b8e706b1a5
After each simulator break, T32Tracer retrieves the latest (16) trace records from the T32. Memory address and value can now be evaluated easily from the trace record. TODO:Nevertheless we still have to traverse the trace to find the instruction causing the access.
102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
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#include "simul.h"
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#include <string.h>
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/**************************************************************************
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Local port structure
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**************************************************************************/
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typedef struct
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{
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simulWord infoBase;
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int bustype;
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int data;
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}
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MemLog_t;
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static int SIMULAPI readCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
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{
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simulWord address = cbs->x.bus.address;
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MemLog_t * memlog = (MemLog_t*)private;
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cbs->x.bus.data = memlog->data;
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simulWord width = cbs->x.bus.width;
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SIMUL_Printf(processor, "MEM Read *0x%x - 0x%x\n", address, memlog->data);
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simulWord data = memlog->data;
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simulWord writeAccess = 0;
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simulWord iadr = memlog->infoBase;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &address);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &data);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &width);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &writeAccess);
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return SIMUL_MEMORY_OK;
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}
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static int SIMULAPI writeCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
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{
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simulWord data = cbs->x.bus.data;
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simulWord address = cbs->x.bus.address;
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MemLog_t * memlog = (MemLog_t*)private;
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memlog->data = cbs->x.bus.data;
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simulWord width = cbs->x.bus.width;
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SIMUL_Printf(processor, "MEM Write *0x%x - 0x%x\n", address, data);
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simulWord writeAccess = 1;
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simulWord iadr = memlog->infoBase;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &address);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &data);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &width);
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iadr += 4;
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SIMUL_WriteMemory(processor, memlog->bustype, &iadr, 4, SIMUL_MEMORY_HIDDEN, &writeAccess);
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return SIMUL_MEMORY_OK;
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}
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static int SIMULAPI PortReset(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
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{
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return SIMUL_RESET_OK;
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}
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/**************************************************************************
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Entry point of the Model
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**************************************************************************/
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int SIMULAPI SIMUL_Init(simulProcessor processor, simulCallbackStruct * cbs)
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{
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MemLog_t *pmemlog;
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strcpy(cbs->x.init.modelname, __DATE__ " MemLogger");
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pmemlog = (MemLog_t *) SIMUL_Alloc(processor, sizeof(MemLog_t));
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// if (cbs->x.init.argc != 3) {
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// SIMUL_Warning(processor, "parameters: <address> <portnumber>");
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// return SIMUL_INIT_FAIL;
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// }
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pmemlog->bustype = cbs->x.init.argpbustype[1];
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pmemlog->infoBase = 0x60000000; // placed at "external RAM"
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simulWord from, to;
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from = 0x20002074;
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to = 0x20002077;
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SIMUL_RegisterResetCallback(processor, PortReset, (simulPtr) pmemlog);
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SIMUL_RegisterBusWriteCallback(processor, writeCB, (simulPtr) pmemlog, pmemlog->bustype, &from, &to);
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SIMUL_RegisterBusReadCallback(processor, readCB, (simulPtr) pmemlog, pmemlog->bustype, &from, &to);
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return SIMUL_INIT_OK;
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}
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