96bc39c05d
The T32 can simulate bare instruction sets without periphery. For the Cortex-M3 we have complete NVIC model including Systick Timer. Currently a simple CiAO can run on the simulator. TODO: - Let memlogger log all memory accesses. - Interact with FailT32 for a complete simulation/FI
119 lines
3.1 KiB
C
119 lines
3.1 KiB
C
#include "nvic.h"
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/*************** SysTick Control and Status Register ***************/
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int STCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.stcsr & (REG_STCSR_COUNTFLAG | REG_STCSR_TICKINT | REG_STCSR_ENABLE | REG_STCSR_CLKSOURCE);
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if (cbs->x.bus.cycletype!=SIMUL_MEMORY_HIDDEN)
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{
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IntCtrl->regs.stcsr &= ~REG_STCSR_COUNTFLAG;
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}
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return BusWrite(&cbs->x.bus, ®);
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}
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int STCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.stcsr;
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BusRead(&cbs->x.bus,®);
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if (reg ^ IntCtrl->regs.stcsr)
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{
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if ((IntCtrl->regs.stcsr & REG_STCSR_ENABLE) ^ (reg & REG_STCSR_ENABLE))
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{
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if (reg & REG_STCSR_ENABLE)
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{
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/* enable timer */
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simulTime time = 1;
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SIMUL_StartTimer(processor, IntCtrl->timer, SIMUL_TIMER_REPEAT | SIMUL_TIMER_CLOCKS, &time);
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IntCtrl->timerrun = 1;
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IntCtrl->regs.stcvr = IntCtrl->regs.strvr;
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}
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else
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{
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/* disable timer */
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SIMUL_StopTimer(processor, IntCtrl->timer);
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IntCtrl->timerrun = 0;
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}
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}
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IntCtrl->regs.stcsr = (IntCtrl->regs.stcsr & ~(REG_STCSR_TICKINT | REG_STCSR_ENABLE | REG_STCSR_COUNTFLAG)) | (reg & (REG_STCSR_TICKINT | REG_STCSR_ENABLE | REG_STCSR_COUNTFLAG)) | REG_STCSR_CLKSOURCE;
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}
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return SIMUL_MEMORY_OK;
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}
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/*************** SysTick Reload Value Register ***************/
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int STRVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.strvr & 0xFFFFFF;
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return BusWrite(&cbs->x.bus, ®);
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}
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int STRVR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus,®);
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IntCtrl->regs.strvr = reg & 0xFFFFFF;
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return SIMUL_MEMORY_OK;
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}
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/*************** SysTick Current Value Register ***************/
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int STCVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.stcvr & 0xFFFFFF;
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return BusWrite(&cbs->x.bus, ®);
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}
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int STCVR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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cbs->x.bus.clocks = 1;
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IntCtrl->regs.stcvr = 0;
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IntCtrl->regs.stcvr &= ~REG_STCSR_COUNTFLAG;
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return SIMUL_MEMORY_OK;
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}
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/*************** SysTick Calibration Value Register ***************/
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int STCLVR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.stclvr;
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return BusWrite(&cbs->x.bus, ®);
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}
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