Commit Graph

5 Commits

Author SHA1 Message Date
f41247b143 gem5: don't count instruction fetch as mem access
Change-Id: I6ea9811c132ef7c235d5a03486ca08afc842b51f
2014-01-06 15:54:02 +01:00
45e0b41022 gem5: restore works now
The function restore(PATH) can now be used to restore a checkpoint.

Change-Id: I25faf9f6335261d2b3ade4185eae93983ece9f97
2013-11-13 17:15:19 +01:00
9c62e4a7f2 - Added signaling of trap situations needed in the weather-monitor to gem5.
- Fixed setting of instruction address for simulator.onMemoryAccess() calls.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2025 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-30 23:59:24 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
b41eec3f65 Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-24 19:18:57 +00:00