Commit Graph

10 Commits

Author SHA1 Message Date
12b539ff75 misc cleanups
This change touches several subsystems, tools and experiments
(sal, util, cmake, import-trace, generic-tracing, nanojpeg), and
changes details not worth separate commits.

Change-Id: Icd1d664d1be5cfc2212dbf77801c271183214d08
2013-09-10 17:37:25 +02:00
4e3c9e3758 sal: CPU now knows extended trace registers
The extended trace register list is needed in multiple locations; the CPU
class is the logical module to contain this information.

Increased number of x86 registers to be traced; we can remove those
that prove unusable for fault-space pruning later on.

Change-Id: Ic46ecdbc55167a6d92872c190317fc0d1a3ad92d
2013-08-27 13:38:40 +02:00
52723a874e sal: allow register sets to overlap
This allows a register to be a member of multiple UniformRegisterSets.
Needed to architecture-specifically store, e.g., a list of registers to
record in traces.

Change-Id: Ia5d20768540efe252a84df967d43e569f107da3a
2013-08-27 13:38:40 +02:00
3cc40e62c7 A few CPUState-related methods should be const (getter)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:22 +00:00
accfba8237 coding-style++, gem5 code doc added
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:18 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
a78911702a Events -> Listeners, waitAny -> resume, addEventAndWait -> addListenerAndResume, ... (refactoring), updated experiments/plugin accordingly, coding-style fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1448 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-12 10:37:54 +00:00
chb
48a83137fa FAIL: Typo in sal/Register.hpp
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1425 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-05 14:37:34 +00:00
5effe564f0 ++coding-style
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1365 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 10:39:05 +00:00
2575604b41 Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00