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e8ec6dc722
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find and use libudis86 properly in l4-sys experiment
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1393 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-29 22:51:18 +00:00 |
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22c5cdbde2
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Adding some code to the L4-Sys experiment, and making it compile again.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1385 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-26 11:37:21 +00:00 |
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09c3f64d51
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Bugfixing in L4-Sys
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1379 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-22 08:56:22 +00:00 |
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58822b02f3
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Some improvements on L4, and correcting a mistake made in revision 1361 (see mailing list).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1377 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-21 14:19:21 +00:00 |
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bff60aeae3
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Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-15 16:39:14 +00:00 |
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f49fa07a25
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Changed BufferCache Backend to STL (as proposed), added IOPortEvent-Cache, updated class diagram
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1325 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-10 19:32:05 +00:00 |
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13cd951a87
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Bugfix in BufferCache, added some security checks, plus minor stuff in doc/howtobuild.txt
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1323 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-09 17:31:32 +00:00 |
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2575604b41
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Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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2012-06-08 20:09:43 +00:00 |
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