Commit Graph

5 Commits

Author SHA1 Message Date
d3d2faf680 globally rename Fail* to FAIL*
Change-Id: Ief2cb687cc69dd92c2e04f9314f0f1347e0a84ed
2016-07-26 17:41:32 +02:00
28fc41da65 Merge branch 'master' of ssh://vamos.informatik.uni-erlangen.de:29418/fail
Change-Id: I35e86d4b367be395121451a86f2731606f43eeff
2013-03-22 16:51:29 +01:00
3c349e06f3 Documentation: Cleanup
Doxygen docu is now build in ${PROJECT_BINARY_DIR}/doc.
(and other small changes.)

Change-Id: I3fef910307e104f120c4f770526c800cfd01a41f
2013-03-22 16:18:58 +01:00
b8e706b1a5 T32SIM: Integrating Tracing feature of the T32SIM.
After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.

TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
2013-03-21 18:57:46 +01:00
96bc39c05d T32 Simulator: Basic Instruction set sim for ARMM3
The T32 can simulate bare instruction sets without periphery.
For the Cortex-M3 we have complete NVIC model including Systick Timer.
Currently a simple CiAO can run on the simulator.

TODO:
 - Let memlogger log all memory accesses.
 - Interact with FailT32 for a complete simulation/FI
2013-03-20 17:17:38 +01:00