fd102c01ea
Important bugfix: passing the instruction cache entry pointer
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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
be9d2912f7
Correction - this _is_ necessary for instruction modification
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1702 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-27 19:50:31 +00:00
765c5f6985
fix restore() in case no "natural" async_events occur
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1410 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-03 12:38:24 +00:00
bff60aeae3
Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-15 16:39:14 +00:00
f74c794789
Bochs tweak: properly handle restore() after TimerEvent
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1331 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-12 15:13:15 +00:00
2575604b41
Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00
