- Gem5 now has two different implementation for breakpoints.
- If only BPSingleListener are used, gem5 Breakpoints are used
- If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
- The register manager is gone. It's functionality is now encapsulated in the
CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
to the CPU state (including registers) and architecture details. The
correspondig objects for the CPUs inside the simulator can be accessed
through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
should fire. The default NULL is used as wildcard for all aviable CPUs. The
events respectively got a ConcreteCPU* member to indicate which CPU really
fired the event.
- For the server, there is CPUArchitecture to access the architecture details.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
- This commit only enables linking against QEMU. The abstraction layer is
completely dysfunctional at this time.
- QEMU's build system needs to be patched in order to create a static
library. This patch is currently not included in the Fail* repository.
- QEMU's JIT compilation may complicate or even preclude the implementation
of some of Fail*'s backend abstractions. Only a minimal subset (serial
I/O, memory, memory writes, save/restore) is planned for the first phase.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1615 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
