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Author	SHA1	Message	Date
Martin Hoffmann	b8e706b1a5	T32SIM: Integrating Tracing feature of the T32SIM. After each simulator break, T32Tracer retrieves the latest (16) trace records from the T32. Memory address and value can now be evaluated easily from the trace record. TODO:Nevertheless we still have to traverse the trace to find the instruction causing the access.	2013-03-21 18:57:46 +01:00
Martin Hoffmann	010137cf54	T32: Updated to recent T32 API.	2013-03-05 17:29:48 +01:00
hoffmann	39a6415001	T32: Integrated Register read/write calls * Tested without connected Lauterbach. T32_* functions are mocked via aspect. * New target t32cli, for sending T32 command cia cli. (for testing) git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a	2013-02-15 18:06:02 +00:00

Author

SHA1

Message

Date

Martin Hoffmann

b8e706b1a5

T32SIM: Integrating Tracing feature of the T32SIM.

After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.

TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.

2013-03-21 18:57:46 +01:00

Martin Hoffmann

010137cf54

T32: Updated to recent T32 API.

2013-03-05 17:29:48 +01:00

hoffmann

39a6415001

T32: Integrated Register read/write calls

* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

2013-02-15 18:06:02 +00:00

3 Commits