Commit Graph

5 Commits

Author SHA1 Message Date
515eb9973b Fail* CPUState: set/getRegisterContent() uses "const Register*" as 1st param
The first parameter (Register* reg) is only used as input (const-correctness).

Change-Id: I5a75a9f7378913e491a8a22872f51a385e910af6
2013-05-07 14:48:36 +02:00
3cc40e62c7 A few CPUState-related methods should be const (getter)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:22 +00:00
cb429fddb2 typos fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2032 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 12:18:47 +00:00
35753cd075 coding style++, some TODOs added.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:27:17 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00