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96bc39c05d85a8d4b0e409c17dd30fc05cd11894
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4 Commits

Author SHA1 Message Date
Martin Hoffmann
96bc39c05d T32 Simulator: Basic Instruction set sim for ARMM3 
The T32 can simulate bare instruction sets without periphery.
For the Cortex-M3 we have complete NVIC model including Systick Timer.
Currently a simple CiAO can run on the simulator.

TODO:
 - Let memlogger log all memory accesses.
 - Interact with FailT32 for a complete simulation/FI
 2013-03-20 17:17:38 +01:00
Martin Hoffmann
010137cf54 T32: Updated to recent T32 API. 2013-03-05 17:29:48 +01:00
hoffmann
d86d18bced T32: Code cleanup. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2104 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-16 22:05:00 +00:00
hoffmann
39a6415001 T32: Integrated Register read/write calls 
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-15 18:06:02 +00:00