523f4a465b
add injection address to results
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Change-Id: I7966f97b8c09bbd6510ca6066dd40be398b54de3
2013-10-21 15:28:07 +02:00
32efc604e7
use MEM FI type
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Change-Id: If149c4fdeaaf6fef96a99d6fe2a424d8ad0f2916
2013-09-11 18:02:02 +02:00
1ca9cb4a52
L4Sys: adapt to DatabaseCampaign
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Change-Id: Ia4912e7a74afccb51f6d704830a2d9c5b5c0159a
2013-08-30 16:06:15 +02:00
2547021e5d
- introduced improved logging in RATFlip
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- adapted the manual
- centralised output conversion
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1988 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-24 12:55:20 +00:00
fd102c01ea
Important bugfix: passing the instruction cache entry pointer
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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
58822b02f3
Some improvements on L4, and correcting a mistake made in revision 1361 (see mailing list).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1377 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 14:19:21 +00:00
bff60aeae3
Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-15 16:39:14 +00:00
2575604b41
Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00
