Commit Graph

11 Commits

Author SHA1 Message Date
d04afaac54 (capstone) feat: add capstone disassembler files 2020-03-16 18:49:44 +01:00
db0b82daca fail: modifications for pandaboard support
Change-Id: I52d3c9b9862b206a000394c45126f0afdfee081f
2014-01-22 17:43:31 +01:00
40f610b536 util: integrate LLVM-based Disassembler
The LLVM Disassembler infrastructure can be used to analyze many kinds
of ELF Binaries. For every instruction the used and defined registers
is available as well as information about the instruction itself.

Change-Id: I9cc89b6c116ceff7b5143a6f179ae31c4e994d2d
2013-07-05 10:19:57 +02:00
03bcf7bfc8 Removed OVP-related (source) files/code (backend discarded).
Change-Id: Ibf8065d9fe760640e5744896b764f9ebb6d2fa69
2013-04-10 15:16:46 +02:00
1fe1dbb3ed util: Added disassembler using objdump tool.
The disassembler disassembles an elf file with
an external objdump tool.
The architecture specific objdump must be configured
via cmake (ARCH_TOOL_PREFIX), e.g. arm-none-eabi- for
arm-none-eabi-objdump.
2013-03-05 21:20:25 +01:00
3501050548 T32: FailT32 support for Cortex-M3
Currently working:
 - Connect/Disconnect, Read CPU info
 - CMM Script generation and T32 startup via cmake (make runt32)
 - Read/Write Register, Read Program Pointer
 - Read/Write Memory
 - Single Breakpoint
 - Setting Memory Breakpoint

TODO:
 - Fix mock aspect for T32_GetRam.
 - Fix Thumb2 bit in function addresses from ELFReader
 - Evaluate memory breakpoint hit
2013-03-01 12:47:32 +01:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
bfedb10cac Starting support for Lauterbach T32 HW Debugger
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1740 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-11 15:25:51 +00:00
hsc
e715149033 first steps towards a QEMU target backend
- This commit only enables linking against QEMU.  The abstraction layer is
  completely dysfunctional at this time.
- QEMU's build system needs to be patched in order to create a static
  library.  This patch is currently not included in the Fail* repository.
- QEMU's JIT compilation may complicate or even preclude the implementation
  of some of Fail*'s backend abstractions.  Only a minimal subset (serial
  I/O, memory, memory writes, save/restore) is planned for the first phase.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1615 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 14:07:03 +00:00
c06565aa4e Basic SAL files and makefile modifications for adding gem5.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1457 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-17 15:35:29 +00:00
2575604b41 Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00